FPGA TDI trace under High-Speed Signal

Hi, Are there anyone here that is familiar with signal integrity concepts? I'm running a trace (TDI for configuration) under a high-speed signal(horizontal) (66Mhz) vertically. Will this signal (TDI) impose a signal integrity problem?

PS: i have other fpga configuration signals running horizontally under a vertical high speed trace?

Thanks.

Reply to
yy7d6
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I assume you mean you are running these signals on adjacent layers. Are the 66MHz signals impedance controlled? if so, then the board stack will show the distances between the layers.

The general rule is that signals at 90 degrees don't interfere with each other (to a close approximation), but if they are sufficiently close, then there will be a discontinuity in the impedance of the track at higher frequencies. What that change actually will be is not possible to know without knowing the board stackup.

TDI can be thought of as a static signal if it is used only for configuration and the 66MHz signals are not running at that time, so the question resolves to 'will this static track with an effective impedance of Rpullup running at 90 degrees to my 66MHz signal cause problems'. The answer to that is 'it depends'.

Got a detailed layout and board stackup?

Cheers

PeteS

Reply to
PeteS

Hi PeteS,

I have 4-layer board w/c has 3 signal layer and 1 split power(POWER/GND) plane as in the image i have provided below.

BTW, routed to the board is n 456-ball fpga, that is why the JTAG traces crossed the signal traces(66-Mhz, PCI-X). Another thing is that other signals used for configuration also completely crossed the 133Mhz signals, as i stated from my previous post.

I have 3 choices for the stackup Layer Pairs Stackup, Internal Layer Pairs, and Build Up stackup,

Checkout this for the stackup info:

formatting link

PS: Can you suggest w/c of the 3 is the best for a 64-bit bus running at 66-Mhz.

Thanks. Yy

Reply to
yy7d6

Now I have a better idea of what's happening:

  1. Have you ever routed PCI-X at 133 before? I have and you need to have solid impedance controlled tracks. For that you need a ground plane. The same goes for 66MHz PCI-X, incidentally.

  1. It is always preferable to have separate power and ground planes. If you must skimp, do it on the power layer (although you still have to have sufficient copper to get the trons where they need to go).

  2. How many targets are there on the PCI-X? At 66MHz you are permitted two (although I am not sure I would suggest it). If it's a single target and you can route from edge balls, you can break out on one layer (although that means splitting the signals across IO bank boundaries)

So - my preferred stack would be

Top ------------------------------ Sig (could be controlled Z)

2 ------------------------------- Power (could be split and even have signals provided they are not near the controlled Z signals) 3 ------------------------------- Ground 4 ------------------------------- Sig (controlled Z) Put PCIX on this layer

Reverse everything for a top breakout of PCI-X, but bottom breakout permits you to via down more easily so you don't use all the routing space by going between BGA balls. To ease the routing, make the pins on the FPGA swappable (except for the ones that have to be fixed) to get the most direct breakout.

Although this can be done on 4 layers, I would strongly consider going to 6 unless every last penny is an issue.

Cheers

PeteS

Reply to
PeteS

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