FPGA config sizes

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We're planning a new universal boot loader for a family of ST
processors. The uP would host the loader in a bit of local flash and
read an outboard serial flash to get the specific application code and
one or more FPGA configurations.

So, how many config bits might there be for a modern mid-range FPGA
doing a moderately complex application?  

I think we could enable compression too.

Please consider this a PHB type question. I don't do FPGA development
myself, past whiteboarding.

--  

John Larkin         Highland Technology, Inc
picosecond timing   precision measurement  

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Re: FPGA config sizes
Am 08.11.19 um 20:08 schrieb John Larkin:
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The size of the programming file is in the data sheet. It is constant
and does not depend on the implemented circuitry.

Newer FPGAs may allow to program only some sectors of the chip.

regards, Gerhard

Re: FPGA config sizes
On Friday, November 8, 2019 at 2:13:18 PM UTC-5, Gerhard Hoffmann wrote:
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I've never used compression on the bit stream, but I recall there is compre
ssion available, possibly even through the tools.  I don't have any direct  
work experience with this, but I have a recollection that most of the bits  
in an FPGA bit stream are zeros.  So some type of a RLL compression may be  
very useful.  

Where have you seen info on programming only parts of chips?  I recall some
 years back Xilinx talked about partial configuration, but they never got t
hat working to the point it was generally available.  I think they worked o
n it for a few large customers and they likely decided it wasn't worth the  
effort.  

Now, instead of programming a part of an FPGA for different tasks, you can  
easily just use multiple FPGAs and program them individually.  Lattice make
s some very tiny FPGA packages.  I mean cell phone tiny.  

--  

  Rick C.

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Re: FPGA config sizes
fredag den 8. november 2019 kl. 20.29.31 UTC+1 skrev Rick C:
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d
ression available, possibly even through the tools.  I don't have any direc
t work experience with this, but I have a recollection that most of the bit
s in an FPGA bit stream are zeros.  So some type of a RLL compression may b
e very useful.  
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the bitstream can make the bit file much smaller depending on how much you  
use of the fpga, but if you decide to encrypt the bitstream and put a key i
n the
fpga you are back at the maximum size




Re: FPGA config sizes
On Friday, November 8, 2019 at 2:09:04 PM UTC-5, John Larkin wrote:
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Anyone know what a "PHB" type question is?  

--  

  Rick C.

  - Get 1,000 miles of free Supercharging
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Re: FPGA config sizes
On 2019-11-08 20:23, Rick C wrote:
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Pointy-Haired Boss, a character from the Dilbert cartoon.
The theme of the cartoon is workplace relations.

Jeroen Belleman


Re: FPGA config sizes
On Friday, November 8, 2019 at 4:32:43 PM UTC-5, Jeroen Belleman wrote:
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Sloman is the model for the 'Wally' character?

Re: FPGA config sizes
On Friday, November 8, 2019 at 4:32:43 PM UTC-5, Jeroen Belleman wrote:
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No wonder a Google search didn't find anything.  Just the reference is obscure enough, using an abbreviation makes it local jargon.  

--  

  Rick C.

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Re: FPGA config sizes
fredag den 8. november 2019 kl. 23.45.40 UTC+1 skrev Rick C:
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I think we are well past the point where a reference to PHB can be considered obscure in engineering circles

https://en.wikipedia.org/wiki/Pointy-haired_Boss



Re: FPGA config sizes
On Friday, November 8, 2019 at 6:07:03 PM UTC-5, Lasse Langwadt Christensen wrote:
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https://lmgtfy.com/?q=phb&s=g

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  Rick C.

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Re: FPGA config sizes
On Friday, November 8, 2019 at 11:09:04 AM UTC-8, John Larkin wrote:
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Page 21:

https://www.xilinx.com/support/documentation/user_guides/ug570-ultrascale-configuration.pdf

Re: FPGA config sizes
On Fri, 8 Nov 2019 11:43:08 -0800 (PST), snipped-for-privacy@gmail.com
wrote:

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I was just wondering what sort of config file sizes people were really
seeing. Maybe compressed, too.

Looks like a 1 or 2 Gbit serial flash is cheap nowadays. I can imagine
storing maybe four configs in the flash chip.



--  

John Larkin         Highland Technology, Inc
picosecond timing   precision measurement  

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Re: FPGA config sizes
fredag den 8. november 2019 kl. 21.20.55 UTC+1 skrev John Larkin:
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http://stm32f4-discovery.net/2014/07/library-21-read-sd-card-fatfs-stm32f4xx-devices/



Re: FPGA config sizes
On Fri, 8 Nov 2019 12:32:39 -0800 (PST), Lasse Langwadt Christensen

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Interesting, but looks like overkill for a little resident boot
loader.

We have used SD cards with Zynq chips, but they already know how to
boot from SD.

https://www.dropbox.com/s/03r1b3zbrqa9lme/P5_SD_1.jpg?raw=1



--  

John Larkin         Highland Technology, Inc
picosecond timing   precision measurement  

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Re: FPGA config sizes
On Fri, 08 Nov 2019 12:20:44 -0800, John Larkin wrote:

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ultrascale-configuration.pdf
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The built-in bitstream compression merely reuses indentical configuration  
frames.  This gives good results on an empty FPGA, but poor results on a  
moderately utilised one.

We use gzip -9 here.  From this thread on the Xilinx forum,  
https://forums.xilinx.com/t5/FPGA-Configuration/Complete-reconfiguration-
with-GZip-ed-bitstream/m-p/667837#M4437
I can see that this gives a compression ranging from 28:1 to 2.8:1, but  
usually about 3.8 : 1 for a typical FPGA.
Please note that ungzipping is only possible in software.  You will not  
be able to use that method if configuring an FPGA directly from a PROM.

Regards,
Allan

Re: FPGA config sizes
On Sat, 09 Nov 2019 01:27:44 -0600, Allan Herriman

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I did a little compression thing, file compressor in PowerBasic and
unpacker in assembly, based on finding runs of 1s or 0s. Typical
compression was 2:1 or better, and the decoder was small and very
fast. It configured most FPGAs faster than the un-compressed version,
because the 1-or-0 unpack bursts were the tightest possible loops.

I wouldn't use that again, because an ARM with hardware SPI or QSPI
interfaces, from serial flash and to the FPGA config pins, would
probably be faster.  



--  

John Larkin         Highland Technology, Inc

lunatic fringe electronics  


Re: FPGA config sizes

iptechnology.com:
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if you don't do you own compression you don't even need to handle the data

just put the DIN,CCLK on the fpga in parallel with the dout and sclk  
on the flash

Give the flash a start address and read command, pulse program on the fpga
and run the spi clk as fast as the flash/fpga an take it, ignoring the data
  


Re: FPGA config sizes
On Sat, 9 Nov 2019 12:27:36 -0800 (PST), Lasse Langwadt Christensen


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I think that would work for us. The uP has a boot loader that finds
the correct code image to copy into the ARM flash, the runtime app. It
only does that once if there is a newer, upgraded code image
available, newer than the factory-ship image. The app then locates the
FPGA image that it wants to run. Users can upgrade in the field.

The uP can bang \PROGB to reset the FPGA. Then we do your thing, read
in the FPGA config from the external flash as fast as we can, but
ignore it. Later we check a register or two to make sure it worked,
and maybe verify the FPGA code version. Only needs one SPI interface
and hardly any code.

I'll try to sell that to the boys and girls.

I think our ARM can do 100 MHz SPI. I have done 50. My 17 mbit Artix7
would configure in way under a second, even uncompressed.

My people are bugging me to use a quad SPI flash, which I prefer to
not do. This pretty much shoots down that idea.



--  

John Larkin         Highland Technology, Inc

lunatic fringe electronics  


Re: FPGA config sizes

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I think the FPGA is also limited to ~100MHz  

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I think you can access most if not all quad SPI flash in single bit mode
so it could still work.

you can also do the configuration in parallel with 8, 16 or 32 bit per cclk
  
with selectmap

the pins could be reused for a faster interface to the MCU after configurat
ion

  


Re: FPGA config sizes
On Sat, 09 Nov 2019 09:29:03 -0800, jlarkin wrote:

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reconfiguration-
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Our experience on Zynqs with nand Flash was that compression made it  
faster, because the nand Flash (as opposed to the decompression or the  
configuration interface) was actually limiting the speed.

Allan

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