Flash ADC encoder logic equations

There may be some tricks, but basically a flash encoder with N bits has

2^N - 1 comparators, that will go off in a pattern of [[M ones] [2^N - M - 1 zeros]]. The logic is just a matter of accurately counting to M, probably while also ignoring patterns that go [1 1 ... 1 1 0 1 0 0 ... 0 0] or similar.

Have you googled "flash ADC circuit" yet?

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Tim Wescott
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You talking about a digital potentiometer?

The way your question is formatted "Flash", that is the only thing I can think of.

For the resolution count.

Res = 2^NumberOfBits;

a 12 bit ADC is common in basic set ups, that would = 4096 different values.

If you're talking about something else, you got me? Etc.

Jamie

h

That pattern "ignoring" scheme is what they call anti-sparkle logic.

This paper has a thermometer decoder towards the end. I'm not sure if anyone ever published their anti-sparkle logic, but it's not that hard to come up with a few schemes. Then again, many people don't know the inside of a logic gate these days. ;-)

Flash converters are notorious for being difficult to drive. A flash converter with the buffer on on-board is worth the money if the specs include the buffer in the testing.

It isn't terribly easy to do that count, it takes order of (M) clock cycles. I think there is a gate tree that does it better, the first (MSB) is obviously the same as comparator number M/2, and the last bit (LSB) is the parity of the ensemble of comparator values. For MSB-1, it's gonna be

( [MSB] ^ {comparator 3M/4]) V ( /[MSB] ^ [comparator M/4])

and you can pretty obviously generate the whole string of M bits in log2(M) time with enough gates.

ash

Flash converters work in one clock cycle, hence the name flash!

Thank you for each of your replies. What I am really after is the priority encoder at the end of the flash ADC, which generates the bits - I would like to verify the Boolean equations for these.

as

...

No, flash converters CAPTURE in one clock cycle, you can pipeline a cascade of subsequent logic so that the result comes out of the output pins several cycles after the capture; there will be multiple captured values in midprocess, and one being captured, and one fully-encoded output, on each clock pulse. So, throughput is one-conversion-per-cycle, but latency of the encoded output may be longer than one cycle.

has

That is one way to build them, but certainly not exclusive. There are applications where latency is not acceptable.

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The last time i did a priority encoder was back in the Tango Schematic = for DOS days. Say 1980s? Not sure if i have any copy of that circuit any more. I think the last time a saw one was for the CD3306 or CD3308. I think they show one in the 8259 programmable interrupt controller as well.