FGPA for deseralization?

I imagine an FPGA could make a pretty simple task of deserializing a bit stream to multiple targets? Basically I want to encode a serial data stream for multiple IC's to reduce the data rate. The idea is that each ic has a "state" and I want to modify that state when needed. The state must be sent to the IC's periodically but fast(they don't have the ability to hold date and must be refreshed quickly).

The FPGA will hold the states the the different IC's and refresh them... but I can communicate with the FPGA and modify the different states when needed. The biggest problem is when I have to completely modify all the states but I'm pretty sure I can find workarounds and it can be done a bit slower.

The point is that I don't want to have to have separate lines for all the IC's running to an offboard uC and having to refresh them continuously. The FGPA would take care of that for me and and the uC can communicate and a easy and leisurely way with the FGPA using just a 1 wire protocol.

Relatively a piece of cake for an FGPA? (about 50Mhz refresh rate for each IC which I think can be all be paralleled in the FGPA so it shouldn't be an issue)

Reply to
Jon Slaughter
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It'd be almost trivial. Monitor your serial input line for a "start" byte (or word), then data 1, data 2, data 3, etc, probably with checksums.

Have the FPGA running your "refresh" thing and when it receives a new data stream, have it do the update.

Have Fun! Rich

Reply to
Rich Grise

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I don't see any reason it cant be done with a relatively small FPGA. If you take this approach i do recommend that you think seriously about the command and status communication structure between the uC and the FPGA.=20

Reply to
JosephKK

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