"Faking" extra resolution with an 8 bit DAC

One method is to use a timer interrupt and an auxiliary variable. Say your desired value is X.Y, where X is between 0 and 255, and Y is the fractional part (another 8 bits for the sake of argument). Using appropriate serialization, set X and Y someplace.

Each time through your timer tick interrupt handler, increment an 8-bit static variable Z. If Z >= Y, set the DAC to X, otherwise set it to X+1.

This won't improve the nonlinearity of the DAC, however. The INL you're more or less stuck with unless you can make a calibration table. To get rid of the DNL well enough that you don't have missing codes in your compound DAC/PWM, you can change the DAC in steps big enough to be guaranteed monotonic--in other words, if you have 2 LSB DNL, just use the upper 6 bits of the DAC, and PWM between X and X+4.

You can also do simple noise-shaping things such as making Y a pseudorandom bit sequence instead of a counter, but there are a few subtleties with that, e.g. you lose the Y=0 code.

Another approach is to use a coarse-fine strategy, summing a DAC output with a normal PWM. That'll make the ripple frequency much higher, but it's harder to get it accurate when you're done.

Cheers

Phil Hobbs

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Dr Philip C D Hobbs
Principal
ElectroOptical Innovations
55 Orchard Rd
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You can apply the standard delta-sigma algorithm to an 8-bit DAC and extend its resolution. Lots of modern audio uses 1-bit DACs.

The problem with extending an 8-bit dac to more bits, using delta-sigma or pwm, is the the differential linearity of an 8-bit dac is likely poor, so the resulting, say, 16-bit dac will have an ugly transfer function. You can fix that by adding some noise dithering to smooth out the codes.

A 1-bit dac doesn't have that DNL problem.

John

Thanks for your reply - I think both approaches might be a viable option for my project. I do like the idea of summing a PWM output to obtain the fractional part, since the microcontroller I'm using already has a hardware PWM output available. I'll do some experimenting with that first, and the first method will be the fallback. The accuracy doesn't need to be great, I just need some "fill in" values to prevent the DAC output "zippering" when ramping up and down.

A first-order sigma-delta modulator is easy-peasy, doesn't take any more code than Phil's first PWM'd version and gives you as much resolution as you want.

You're still left with the issues of DNL, so check your data sheets. For control loops all you really need is monotonicity, and I think most

8-bit DACs have that these days unless they're really fast.

Most of the time that I use this technique it's for a PWM output that just needs a bit of extra resolution, so DNL simply isn't an issue -- the issues that come next are usually power consumption and residual noise, and they're usually not a big deal if you were coming close with your PWM output.

I've even used this technique to get an audio output from a single FPGA pin -- all that I was shooting for was something as good as a monitor speaker on a modem, and I got better than that so I stopped. If I really needed good quality I'd do two things: first, I'd use at least a

2nd-order modulator, and maybe 3rd-order or 2nd-order with some noise injection to break up tones; second, I'd seriously consider having the FPGA drive an analog switch or whatever the coolest CMOS single-gate logic was, as a buffer, with its own super-clean supply and a very light resistive load into the low-pass filter.

Here's an article. I wrote it, so it must be good :-) :

If that link's too long, here's a page on my site pointing to the article:

And some other articles that you may find interesting:

--

Tim Wescott
Wescott Design Services
http://www.wescottdesign.com

Do you need to implement control loops in software?
"Applied Control Theory for Embedded Systems" was written for you.
See details at http://www.wescottdesign.com/actfes/actfes.html

Nice article. I've been wanting to try that out, and I actually have the opportunity this coming week, assuming my head clears up enough to do coding.

(This is the first bad cold I've had in two or three years, so I can't complain too loudly. Slagging people off on Usenet takes many fewer coordinated brain cells, fortunately.) ;)

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs
Principal
ElectroOptical Innovations
55 Orchard Rd
Briarcliff Manor NY 10510
845-480-2058

email: hobbs (atsign) electrooptical (period) net
http://electrooptical.net

+1.

You'd be better off using the PWM output for the most significant bits, and using the eight-bit DAC for the lower order bits. It isn't all that difficult to to make an eight-bit PWM output where the individual levels are accurate to 12-bits or better, and the advantage of limiting the PWM to coarse quantisation is that low pass filter required to get rid of the switching noise has a realitively high 3dB point, which measn that you can use small capacitors - polypropylene or poly-styrene - with good stability and very little charge soak.

-- Bill Sloman, Nijmegen

[snip] [snip]

I would hope so. I was building monolithic 8-bit DAC's in the '60's with guaranteed monotonicity.

...Jim Thompson

--
| James E.Thompson, CTO                            |    mens     |
| Analog Innovations, Inc.                         |     et      |
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| Phoenix, Arizona  85048    Skype: Contacts Only  |             |
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      Remember: Once you go over the hill, you pick up speed

What about ripple?

John

As a practical example, you could take a look at the PWM code used by the VE2ZAZ frequency controller (which disciplines a 10 MHz VXCO based on the pulse-per-second output from a GPS receiver).

It extends the precision of a PIC's PWM output by a couple of bits, by alternating between values. The resulting output goes through a low-pass filter to average out the signal.

The same basic trick can be used for non-PWM DACs... just alternate between values periodically, and feed the output through a low-pass filter whose time constant is comfortably longer than your alternation cycle time.

If you extend this approach to its extremes, you get a "1-bit DAC" such as are used in many modern CD players. At that point, the algorithm you use to derive the value-alternation pattern becomes quite important, as the proper "noise shaping" algorithm will move the noise created by this process up to high frequencies where it's more easily eliminated by the low-pass filter.

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Dave Platt                                    AE6EO
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  I do _not_ wish to receive unsolicited commercial email, and I will
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It's cheap but it's hard to filter. Terrible hangovers too.

-- Cheers, James Arthur

Almost as bad as Thunderbird ;-) ...Jim Thompson

--
| James E.Thompson, CTO                            |    mens     |
| Analog Innovations, Inc.                         |     et      |
| Analog/Mixed-Signal ASIC's and Discrete Systems  |    manus    |
| Phoenix, Arizona  85048    Skype: Contacts Only  |             |
| Voice:(480)460-2350  Fax: Available upon request |  Brass Rat  |
| E-mail Icon at http://www.analog-innovations.com |    1962     |

      Remember: Once you go over the hill, you pick up speed

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That's what the low-pass output filter is there to block. Worst case output ripple is usually at 50% of full scale output and you typically aim for enough attentuation to get the residual ripple below the LSB. I've used two, three or or four poles of attenuation optimised for minimum settling time in various different applications - the first one back in 1975. Four poles costs more, but settles faster if you do it right.

-- Bill Sloman, Nijmegen

It's not that hard, though it can get expensive aand a bit messy if you want a lot of bits of resolution, and have to start filtering the power rails to keep the clock noise out of the analog output.

You do have to design a fast-settling low pass filter, but Williams and Taylor tell you how to do that.

-- Bill Sloman, Nijmegen

Once, Fred Sanford mixed some with Champagne - he called it "Champipple."

Cheers! Rich

If you use PWM for the 8 MSBs, and add in an 8-bit real dac for LSBs, the PWM had better have 16-bit-quality ripple, namely 16 PPM turf, or the whole thing becomes silly. And if you use a filter to get the PWM ripple down that low, you're inevitably adding a lot of delay. It gets messy to splice the 8 bits of PWM to the 8 bits of fast DAC without either making awful transient glitches or using a very, very slow filter.

A "relatively high 3 dB point" can't fix that dilemma.

It's all in the numbers, of course.

If you run PWM at high frequencies, and want high accuracy, the edge rates start to matter.

Consider a 24-bit delta-sigma ADC running at a 64 KHz clock rate. It's making internal feedback pulses that are multiples of 15 microseconds wide. If the widths are accurate to even 20 bits, that means they are accurate to about 15 picoseconds. At 24 bits, below 1 ps. All of which leads me to think they actually do some sort of charge dispensing tricks, and not the simple current steering they show in the block diagrams. Does anybody know how that actually works?

John

Isn't that more like dithering your values?

Actually, I think most average ADC's will jump between their steps if you try to maintain a value. It's a matter of averaging those if you want to simulate higher res.. It would have to be a very low res ADC to be able to hold it steady on one value, at least with most sources I deal with.. Maybe you're trying to work with super stable sources.

But, if you're not into the actual coding of the ADC in the uC, internally, maybe you don't have that option.

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Why? The delay through a critically damped low-pass filter is entirely predictable - you just change the low order bits for the fast DAC that much later than the numbers controlling the PWM that decodes the high order bits.

Obviously not. It does make for a smaller delay, which is easier to fix. There's no dilemma because there is just one problem and one - obvious and perfectly practicable - solution to that problem.

Surprise, surprise.

Provided that output slews fast enough to get from one rail to the other before tha next transition comes along, the edge rates don't matter all that much. If two edges close together slew at different rates from two edges further apart, or rising edges slew at a different rate from falling edges then the PWM DAC isn't perfect, but not usually all that far from perfect.

Why? In the context eight bits is about as many as you might want to consider

-- Bill Sloman, Nimegen

Champipple is Ripple and Pink Champale.

That idea certainly seems to work in one of my applications where I multiply the A/D value by two and by the time the averaged value gets to the LCD display, I get back my missing in-between values.

boB