Example Use of CD4059 Divide by N

This does have to be programmed with binary numbers, but the slightly more intuitive 74HC40102 seems to have been discontinued (at least by NXP).

Concentrate on P4-6.

Basically you setup in BCD format the N you want into the jam inputs and then choose a prescaler with Ka=Kb=Kc=1 as /1 for simplest case.

Dunno. I still remember checking code to do this decades ago.

Still available from Digikey, but it appears to be much the same in function.

This looks interesting.

Mike Towner

I think you're getting to something that's complicated enough that programming just isn't going to be really intuitive. It's one of those things that will have you buried in reams of scratch paper with scribbles and crossed-out bits and cuss words and all before you're done.

Why use such an old part? You're dooming yourself either to thumbwheels or a parallel interface from a microprocessor, when there's a good chance that a microcontroller with an on-board counter could do the whole job.

If you can't understand that simple datasheet then you can't understand anything.

How about this one?

If you explain your needs in more detail maybe we can show you how to do it?

You might enjoy reading Don Lancaster's "CMOS Cookbook". It's sort of a Cook's tour through the CD4xxx series, with a cheat sheet for each part and a bunch of applications advice, such as divide-by-N counters.

I learned a lot from it in the long ago.

Cheers

Phil Hobbs

I really had to look twice that I am not responding to a 30-40 years old request.

Anyway, there are at least two ways to implement a divide by N circuit:

• Use a ripple up counter with gatings to detect when N is at the counter output and generate an asynchronous reset to all flip-flops. Of course, any ripple counter will suffer from asynchronous reset timing problems, limiting the maximum clock frequency.

• Use a synchronous down counter and parallel load N into the registers when the counters reach 0. In fact the Pre load N might be ready to be pre loaded, when the counter reaches 1 or even 2, thus a preloadable synchronous down counter will operate at higher frequencies than a divide-by-N asynchronous ripple counters.

In the 1970's the CMOS counters were much slower than TTL ripple counters, so they tried to get every means to have reliable CMOS counters at comparable frequencies.

What I asked for was one example of the practical use of a CD4059 to help me understand the "simple" data sheet above. IOW pin connections.

For example, divide 32.768KHz down to around 14 Hz.

I would then build it and better understand the process.

Any chip that is not a micro that performs this type of function better would also be of interest.

Thank you,

Mike Towner

To be honest, this is a complicated chip to use. But I think I understand it. First problem, it will only divide a frequency by an integer to get another frequency. I think I can make it divide by 2341 to give you 13.99743699274 Hz. There are fractional dividers which will give you exactly 14 Hz.

To get a divisor of 2341 we choose a divisor for the first stage from the list of 2, 4, 5, 8 or 10. Using 5 requires the use of "Master Preset" so I pick 4. This means we need to set the mode select to 011 (Ka through Kc). Dividing our divisor of 2341 by 4 gives 585 with a remainder of 1. The remainder is used to set the Jam preset of the first stage so J1 = 1 and J2 = 0 (only two bits are set because of the first stage divisor we picked using the mode select). Jam presets J3 and J4 are used for the most significant digit of the quotient which in this case is 0, so both J3 and J4 are 0. The remaining digits of the quotient are used to set the rest of the Jam presets. So J5 through J16 are set to form 585 in BCD with J16 being the most significant bit.

Change the J1 preset to a 0 and you divide by 2340 eve to give you

I can't be sure, but I think that is right. Make sense now? Can anyone confirm I did this right?

A fractional divider works by dividing by N and N+1 in the right ratio to give the exact ratio of frequencies. The period of the output varies by one clock cycle though, so it has phase noise and such.

Here are a couple links that will show how to use the CD5059 in a couple basic synthesizers, and gives a bit of theory of operation for you in preparation for building the circuit.

http://213.114.130.173/use/synth-00.htm http://213.114.130.173/conv/synth-10.htm

Review those projects, then come back with any questions that you have.

Cheers, Dave M

Mike Towner wrote:

Good to hear I am not the only one to think so.

Thank you for your detailed explanation. It is starting to make sense to me now. I always liked the old text books where they gave you a concrete example.

I have drawn the digram (below) and will built it up this weekend.

Mike Towner

Everything I gave you I got from the data sheet you referred me to. It has several examples.

Your example was better. Thanks.

Mike Towner

Yes, I had trouble reading theirs at first. Glad I could help.