IC1-B is a "square wave" oscillator. Since there are no values on the drawing, no way to determine the intended frequency and duty cycle of the oscillator.
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Dave M
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"In theory, there isn\'t any difference between theory and practice. In
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Ah ..... of course the omnipotent (well versatile, as i am learning) opamp. I knew i must be missing something as someone said this schemat is not too bad.
i only made it about three pages into the datasheet originally but when i read your reply i went to page 19 there was an exmple of using as an oscillator.
IC1-B is a square wave generator due to the hysteresis design with the feed back to the (+) input. C3 makes up for the timing frequency used.
The circuit is using the raising edge of the square wave as the time domain for acquiring readings. Initial raise will only be seen in the IC1-D circuit due to the small size of C4. R7 will discharge it quickly.
In the bridge it self, if the Test cap has some (R) in it, R9,R9 will not be at abs 0 volts. The offset is quickly reproduced and amplified via the IC1-C. Because this is the starting of the square wave from the generator, C4 will see a sharp raise in the signal and thus C4 being small like it is, will produce a nice short pulse of the amplitude that translates to an ohm reading via the IC1-D. After this initial starting pulse, there will be a continuous reference as a ramp how ever, this will have little effect. A perfect cap with 0 ESR, should never allow the sharp raise of the generate be seen at C4. All you should get is a 0 to 4.5 volt ramp at best. But in a cap that has some ESR, the starting ramp will not be at
0(R9+R10) and this is where the IC1-C will amplify it greatly at the same time the initial raising of the square wave. DS3 anc C6 will simply hold a reference for you, between cycles.
I know that is long winded but I think at times it's needed.
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Tanks Ed, I am amateur occasional electronics hobbyist trying to learn more.
i expect this to be quite easy on my wallet as i plan to use all salvaged components,(because it makes it more interesting for me) i have found all the components i need on a modem/hard drive controller /video card boards now for the even more fun part....
I don't like it, that meter is more wishful thinking than anything else. We had a meter design contest going here, but it was ruined by the non-producers, rejects, delusional narcissists, and trouble-makers, so you're not going to get anything useful from this newsgroup.
That's right, Fred, and we're still waiting for your design to be submitted. You can either submit it, or continue to be a non-producer. You contributed nothing, yet you damned everyone else's design ideas until you killed it off.
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Michael A. Terrell
Central Florida
Hilarious. Here I sit, piggybacking on some local signal with my laptop, in the back room of a coffee shop in Brooklyn, surrounded by middle age men speaking Italian and playing cards. I was almost tempted to ask one of them to translate the words above the circuit diagram... almost.
I know next to nothing about this, so I don't have an answer. I do have a very simple question. At 100 kHz, wouldn't say a .1 uF cap have high enough reactance to swamp the ESR? Seems like you'd need megahertz, maybe even hundreds of megahertz, to be sure the resistive component of a small ceramic cap's impedance would exceed its capacitive component by order(s) of magnitude. But maybe then ESL would interfere... I'm just a babe in the woods guys, don't toast me.
On a sunny day (Tue, 25 Dec 2007 10:19:46 -0800 (PST)) it happened gearhead wrote in :
It is not the frequency, it is the rise time of the square wave. If the wave rises in 1 femto second, the frequency can still be 1 Hz only. For a capacitor, to charge in a short time the formula Q = C x U = i x t shows that the voltage across the cap is U = (i x t) / C For normal values of 'i' and very short 't', U will be close to zero.
A typical example:
1 uF, 1 us time, 1 mA, then after 1 uS the voltage across the cap will be: U = 1 mA x 1 uS / 1 uF = 1 mV U = .001 x .000001 / .000001 = .001 V
For a circuit like this:
Uin ----- C ------- out | R1 | ///
For an input voltage change like this: ________________________________________ | | | | _|
The voltage across the resistor will look like this:
peak = Uin |\ | \ | \ | \ _| \_________________
If the capacitor has internal loss in th2 form of a resistance for example, then there is a voltage divider, and the circuit looks like this:
U in ---R2 - C ------- out | R1 | ///
The peak output is now no longer Uin, but R1 / (R1 + R2) x Uin.
Okay, the OP's circuit uses a voltage divider like you described (actually some kind of bridge arrangement) and a peak hold. It makes sense that you need a fast-rising edge, to keep delta V on the cap low enough to maintain a linear relationship to C. But you need so much speed to do this, that I wonder if the cap's inductance will affect the measurement. If so, perhaps one could design a circuit that uses a longer charging time, factoring in the exponential behavior of a capacitor when it charges; do the whole thing much, much slower, pretty much eliminating any inductive effects and reducing errors due to the slowness of the op amps. I guess the circuit specifies fet op amps for their speed, but still, are they fast enough for this. Just glancing at the TL084 on digikey, it looks like they have slew rates in the neighborhood of 15 V/uS...
It works. It's not wishful thinking. Whether you, or I, or anyone likes it or not is irrelevant. A better idea, or proof that it does not work would be relevant.
On a sunny day (Tue, 25 Dec 2007 12:55:26 -0800 (PST)) it happened gearhead wrote in :
You mean to R?
If the cap is inductive is is also defective :-) Some rolled foil caps, where the contact on the side of the foil gets lose, can make inductors. The circuit detects series 'impedance' in a sense. In a good capacitor series impedance is close to zero.
All right, let me see if I get this. For the purpose of understanding the circuit, the real capacitor under test is modeled as a resistor in series with an ideal capacitor. By design, the circuit measures series resistance Rs by using it to unbalance a bridge. For this to work, the circuit has to see Rs as having one end connected to the bridge and the other end connected to ground. Thus series capacitance Cs has to be invisible to the circuit. It has to look like a short. The circuit demands the capacitor look like a short by by having the pulse so fast, and the charge taken on by the capacitor so insignificant, that there is effectively no change in the capacitor's voltage. Otherwise, it corrupts the measurement. That's what I meant about the need for the "fast-rising edge." Is the circuit so fast that picofarad caps won't take on some small voltage?
By "cap's inductance" I meant _parasitic_ inductance, and the inductance in the cap itself may only be a small part of the total parasitic inductance of leads, binding posts, wires connecting them to the circuit board, and traces. Or even jumpers and alligator clips. This is after all a hobbyist project.
I used SPICE to simulate the important parts of the circuit composed of the bridge and IC1-C and IC1-D. I used a pulse generator rather than IC1-B. I used voltage-controlled-voltage-sources rather than op-amp models. I looked up an arbitrary capacitor's ESR for this simulation.
I got the following output "indications" vs capacitor (arbitrarily 100uF) ESR:
So, the circuit appears to work, but it depends on what you are expecting from it as to how well it works. If you decide that anything below, say, 50% is bad, you may not catch the capacitor that causes equipment to fail when it has more than 1.8 to 18 ohms of ESR.
I think the amount of ESR that can be tolerated will depend on the target equipment's sensitivity to ESR. In some cases, you may find that even 1.8 ohms causes malfunction. In other cases you may find that 1K ohms of ESR causes no problems.
To verify the simulation, you could build the meter and test various capacitors known to be new and good. Then add some series resistance to each and record the readings. Then all you would need is experience to know when equipment will fail due to high ESR.
On a sunny day (Tue, 25 Dec 2007 22:11:21 -0800 (PST)) it happened gearhead wrote in :
Right, and it uses a peak detector approach, so the slowly decaying waveform part is not used.
OK, after posting the previous reply, it occured to me I could have misunderstood the remark about inductive. Indeed, if you used an almost infinite fast rising edge, any inductance, even the capacitor leads, would be seen, and a cap could be rated bad, while it actually was not. In this circuit however, the pulse comes from the output of an opamp oscillator, and those have reasonably slow rise times, micro seconds rather then femto seconds, and so we do not have to worry about very small inductances.
Indeed there is a useful range of capacitor values where it will work. I think the ESR meter, in this case, is mainly used for electrolytic capacitors, so maybe from 1uF up?
Funny, I did the same thing for the Ludens-type meter. It seemed it could benefit from a better opamp in order to work at
100KHz. So I took an TLC272. Also the detector diodes were replaced by
1n5818's. Shunt resistors were lowered from 10 to 4.7ohm to improve headroom a bit in the low-ESR range. Simulation then gives: scale ESR
100 0
97.74 0.1
95.59 0.2
89.56 0.5
80.93 1
67.55 2
44.18 5
26.82 10
13.74 20
4.21 50
1.34 100
Although this is not a binary group, I took the liberty to append a small image of what this would do for a meter scale.
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