The LM1117 data sheet shows thermal resistances for the DPAK mounted on various copper patterns. They got from 104 to 47 K/w.
I did some measurements on an old board. This is a 6-layer board with layer 3 ground plane. Temps are package top as seen on an IR imager.
No vias, so all the cooling is from the layer 1 copper.
That one has vias and pours on 1, 2, and 6.
This could be better. I hand-soldered the chips and I doubt that I got full solder flow under the tabs. Layer 2 ground plane would be better, too.
So the National thing is pessimistic compared to what you can do on a multilayer board.