does this make sense?

It doesn't really make much sense.

The cost of making a mask set for an integrated circuit used to be upwards of $100,000, so precise simulation is correspondingly important to make sure that this money is not wasted.

The up-front cost of making a PCB is a lot lower, and we can afford to live with less precise models that run a lot faster on much cheaper computing hardware, sometimes merely the stuff between our ears.

Sort of an off-the-wall conclusion, but a lot of it is true... I design really hairy chips with THOUSANDS of transistors... and they always work, because the models from TSMC, XFAB, etc., are marvelously accurate. I haven't had a chip not work first time out of the foundry in more than thirty years.

The real truth is that, at the chip level, circuits aren't designed at the OpAmp level, they're designed device-by-device... internally you don't need all the bells and whistles and protection circuits to avoid what a PCB jockey might do to damage them.

The other truth is rather sad... you're only going to be able to simulate jelly-bean parts on the manufacturer's simulator. Note how many Linear part Spice models are encrypted, and can only be simulated on LTspice. Analog Devices is heading the same way, only there you'll have to simulate in the "cloud", via the web... I know, I almost became a part of that scheme.

What are you going to do when you have a design with both Linear and Analog Devices parts? How will you simulate the combo?

Welcome to the twisted future >:-} ...Jim Thompson

What a maroon. Of course we'll all just have RJ45s surgically implanted in our heads, so all that squishy analogue stuff can just go away.

Cheers

Phil Hobbs

He's just trying to meet a quota for submitted articles, it is not the product of a lifetime of profound thinking on the subject matter. Drivel IOW, "don't you pay it no mind."

He is a maroon.

But it's interesting that we do still solder parts onto slabs of copperclad, etched fiberglass, like everyone did 50 years ago.

Yeah, that's what I was thinking. "SENIOR IC design"? Sheesh, I don't want to read what the JUNIOR IC design guy is writing about.

Well, we have done some mostly analog ASICs, trying to put very low noise charge integrating amps on standard CMOS processes. The design files were MASSIVELY optimistic on 1/f noise. Our circuits worked, for the most part, but there were some quirks to work around by adding stuff on the board. I was the guy who had to figure out what was wrong and see if I could engineer my way around the quirks.

But, unless you have a lot of constraints pushing you to integrate the thing, it doesn't make sense to design an ASIC. One constraint is size, another is production volume. If you are making millions, it makes more sense to incur the risk of respins and engineering time. That's a different world than I work in. Size mostly drove us to make ASICs, we have only made barely 1000 ICs, I think, at MOSIS.

Jon

Isn't anybody capable of copying them also able to slice one open and figure it out? It's not as if they have to look through 10 layers of metal.

I'm contemplating a retirement income scheme based on making non-encrypted models... that'll really aggravate them >:-} ...Jim Thompson

Reverse engineering of analog layouts is done all the time, though mostly for patent violation checks. Most reverse engineering is done to look at the topology.

But say yo did want to create a spice netlist. The processes are proprietary to the semi. You would have to model the devices somehow. And it isn't like you will have a raw wafer with a test pattern. You would have to take a product die and hack it to model the process.

You can miss tricks like the use of fets with different thresholds, which is hard to spot if it is just a matter of using a different implant mask or perhaps none at all (native device).

There's a TL431 model floating around, based on the original equivalent circuit that used to be in the datasheet (some manufacturers still provide it). Apparently it's a good fit to the real thing, don't know how much device modeling was done with it.

Official behavioral models of the thing are, of course, notoriously awful.

Tim

No. It blatantly ignores the economics of the situation, mask sets are expensive. It also ignores that no matter how spiffy the IC is, its performance can be lost due to poor board layout/design. Not to mention there is always call for new arrangements of standard per little IC function.

?-)