Digital Multiplier Design -Help

No comments or hints -- just some questions that you need to ask before you can proceed intelligently.

Which part do you need to design?

You indicate the technology, but surely you aren't planning on laying it out at the transistor level -- or are you? If not, then shouldn't you just write verilog or vhdl code for it? Perhaps you'd want to optimize it for the technology, but for the most part wouldn't you want something that would synthesize on nearly anything?

Is it going to be one huge combinatorial thing? Do you want it to be pipelined with some number of stages of delay but the ability to run things though once per clock? Do you have a time limit? Do you want it to be a state machine that takes multiple clocks to do one multiplication and the using process has to wait on it? Will it operate on signed numbers or unsigned? What signed format will you use (2's complement, 1's complement, sign magitude, something else)? Will you be returning a 16 bit answer? 32? Perhaps 31 if it's signed (why does that make sense)?

------------------------------------------- Tim Wescott Wescott Design Services

Thanks for your reply Tim. My prof says I have to design a 64 bit (not

16 bit--sorry abt the typo) input vector full custom design multiplier ie at transistor level using cadence tools. Is it a good project to do? If not, can you help me choose what I should do as project (MSEE)? I am good at cadence tools and I would prefer to do some design work.

The subjects I have done are as follows: CMOS Digital Circuits, ASIC CMOS Design, Mixed Signal Design, Digital Design using Verilog, Advanced Logic Design, Advanced computer Architecture.

Meghana.

You saw me exercise just about all my knowledge of digital circuit design in my previous reply. To you a chip is something you design. To me a chip is a little black thing with metal pieces sticking out that I know how to use effectively.

So I can't really suggest anything specific. This does sound like a project that will demonstrate competance over a range of subjects if you pull it off. If you _do_ pursue this project, however, I would suggest that you work at it in stages:

1. Get it more fully specified. "64 bit input vector multiplier" is still not specific enough for me to be able to use it. This is a student project so you should probably specify it yourself and then run it by your prof to see what his expectations are.
2. Decide what architecture you're going to use. I gave you three very different candidate methods to choose from, with three very different tradeoffs between real estate, design time, chip cost and execution time. Make sure your prof agrees with your choice -- you don't want to make an itty bitty cheap slow thing that would sell like hotcakes in a 1. Get it more fully specified. "64 bit input vector multiplier" is still not specific enough for me to be able to use it. This is a student project so you should probably specify it yourself and then run it by your prof to see what his expectations are. 2. Decide what architecture you're going to use. I gave you three very different candidate methods to choose from, with three very different tradeoffs between real estate, design time, chip cost and execution time. Make sure your prof agrees with your choice -- you don't want to make an itty bitty cheap slow thing that would sell like hotcakes in a $0.50 cent ASIC when he was looking for something to stick into a supercomputer -- nor do you want to do the opposite..50 cent ASIC when he was looking for something to stick into a supercomputer -- nor do you want to do the opposite.

2a. Do a literature search. Multiplier architectures are (or were a few years ago) a hot topic in the IEEE Circuits and Systems society, or at least they were. There's been a lot of effort dedicated to this, and the articles that I've seen I've almost been able to understand -- and as I said I'm not a chip designer. You may even get some full-blown design down to the transistor level that you can (with your prof's approval) adapt to his requirements.

1. Understand how it's supposed to work at an abstract level before you start slinging transistors. I would get it working fully at the RTL level before I even considered going down to the gate or transistor level.
2. Once you've completed steps 1-3 _then_ start thinking about how you could streamline it for speed, size, cost -- whatever you want to optimize for.

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Tim Wescott
Wescott Design Services
http://www.wescottdesign.com