Hello all, I recently had to modify an FPGA based board to add a couple of LVDS clock lines between neighbouring FPGAs (about 100mm long and working at 150MHz). The existing clocks, in the PCB layer stack, were single ended and suffering from severe cross-talk from adjacent data lines. The new connections used previously unused and unconnected pins.
My first prototype was made using fine enamel wire, twisted to keep the wires in close contact and to provide some rigidity to the wire mod. This appeared to work fine and I remember 'scoping up the receive end and seeing nice monotonic signals. All tickety boo until we made a stitch on 0.2mm thick PCB which basically solders on to vias to do the same job in a much neater and easier way from a production point of view. Being on a single sided PCB, the tracks were routed
0.1mm spacing and track width with about 5mm between adjacent pairs for safety. The PCB sits directly on top of the back face of the board over a solid ground plane (for the most part excepting where it sits over the FPGA vias to gain access to the required vias).The signals now look different so I think I have changed the impedance radically. The received signal is now more square like with a small amount of ringing (though not excessive).
So my question is, can anyone explain what might have happened/what differences should be expected between the two types of mod?
BTW the receive end has an on-chip differential term of around 100 ohms.
Many thanks,