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Design play/challenge: Phase Shift PWM

It finally occurred to me, I've been using these things for so long, yet never built my own. And therefore, never fully understood nor trusted what the documentation says (or hides!).

So here's the challenge:

Design a phase shift PWM controller.

Example applications: Full bridge forward converter (SMPS, UPS, motor control, etc.) Frequency-locked, resonant systems (resonant SMPS, induction heating): PWM provides linear, continuous power control, independent of frequency.

Requirements:

- Constant 50% +/- 3% duty cycle per output (complementary outputs with dead time for full bridge gate driving are easily added on)

- Variable frequency, using a control voltage/current, or single variable resistor (duty cycle and phase shift remain ~constant)

- Variable phase shift, from a control voltage input

- Phase shift adjustable from 0-180 degrees or more (or 180-360, same thing)

- Must use continuous-time methods, not sampled/divided. (Or, ENOB > 12, which will rule out most digital methods for rather modest output frequencies anyway.)

- Uses discrete transistors, comparators, logic gates (no more than MSI), that sort of thing. ("Transistors" includes the hollow FET kinds, if you like.)

Homework: The basic prototype is an astable multivibrator (makes 50% duty cycle reference clock), followed by a delay and ramp circuit. The tricky parts are:

- The multivibrator has to be timed from the same global (frequency control) bias current (e.g., using a current steering triangle-wave oscillator, like you'd find in an analog function generator)

- Essentially, an oscilloscope's triggered sweep circuit is required for the delay generator. Multivibrator triggers it on rising edge; cap charges for almost the whole cycle time (again, charged by the global bias current), making a sawtooth wave; comparator picks a point along that ramp, thus implementing the delay.

- Thus, delay is adjustable anywhere along the sawtooth ramp, which might be, say, 10-350 degrees. It can't go quite to zero due to delay (which could be subtracted out by delaying the original clock source), and can't quite go to 360 because of reset time and trigger window.

- To square up the output, a 50% duty cycle generator is needed, which can be: injection locked multivibrator (otherwise matched to the clock multivibrator); or another triggered delay generator with the required slope; or:

- Or instead of using a triggered sweep for the delay generator, the clock multivibrator can be a sawtooth type. Use one comparator to bisect the sawtooth, yielding the non-delayed 50% output. Use another comparator to generate the delayed trigger (the multivibrator slope sets range). A triggered delay generator is still required, to produce the delayed 50% duty output.

- Symmetry bonus: you can start with a clock pulse, and run two triggered delay generators, where one delay control voltage is inverse of the other. Each one only needs 90 degrees of adjustable range. This probably incurs more hardware than the lopsided-phase version, though.

Possibly useful: 50% duty can be obtained by dividing a square wave in half (type T flip-flop), without having to match capacitors. But half the frequency means twice the phase shift, and if the flip-flops ever end up out of sync, phase suddenly inverts. May be tricky to use.

The basic breadboarding of this ("RTA level") description used an LM339,

5/6ths CD40106, 1/2 CD4013, and five transistors (true, I could've better squared up an edge using /Seven Transistors/..). On a good old fashioned solderless breadboard, that's a full row of stuff. Very messy!

So if I've captured your fancy at all... Simplify it, if you think you can! ;-)

(Special note to you in the monolithic peanut-gallery: yes, I know you can make all of this, and more, in a tiny 1mm chip. Unless you have one available that can be bought for less than the parts listed above, STFU. :-P )

Tim

--
Seven Transistor Labs, LLC 
Electrical Engineering Consultation and Contract Design 
Website: http://seventransistorlabs.com
Reply to
Tim Williams
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Make an analytic (sine+cosine) sine wave oscillator and combine the sine and cosine outputs with a two-phase resolver for phase shift. Using a Scott T-transformer, even a three phase synchro will do.

--

-TV
Reply to
Tauno Voipio

I would like to challenge not using a micro. If you use a micro with 1Msa 12 bit ADC and feed that with DMA to the frequency setting register, wouldn't that be possible. Even if you have to let the micro do nothing else than this task?

Cheers

Klaus

Reply to
Klaus Kragelund

Still won't meet the continuity requirement. Maybe not bad if you have one with a vernier timer.

But anyway, you aren't learning anything, which defeats the purpose of a design _play_. ;)

Tim

--
Seven Transistor Labs, LLC 
Electrical Engineering Consultation and Contract Design 
Website: http://seventransistorlabs.com
Reply to
Tim Williams

On a sunny day (Tue, 16 Feb 2016 14:05:20 -0800 (PST)) it happened Klaus Kragelund wrote in :

Yep, 2$ PIC can do all that.

Reply to
Jan Panteltje

Here is the way I'd start doing it using jelly-bean parts:

I haven't included the deadtime/overlap requirement which if only a few

00's ns could be RCD delays in the gate drivers. The frequency can be tuned by one resistor. Duty cycle is 50% guaranteed by flip-flops.

With more thought I might cross-couple the flip-flops to prevent the phase flip-over risk you mention. Not yet sure this even works! but looks easy enough to spice or breadboard.

How did you do it?

piglet

Reply to
piglet

o:

Freescale 56F84xxx DSCs have it:

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/dsp-dsc/dscs:DSC_HOME

probably also other of the family.

Bye Jack

Reply to
jack4747

Hmm, delay comparator only covers half a wave at the initial clock, so 1/4 wave at the output, no? In other words, only about 90 degrees of range, not 180?

My first attempt did: Sawtooth osc Comparator (sawtooth + fixed threshold) for 50% duty (non-delayed output) Comparator (sawtooth + adj threshold) for adjustable delay (say 10-350 degrees) Triggered ramp generator (aka monostable timer) for 50% duty (delayed output).

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The crossed-out part was as-built, then I realized I could skip the runt-pulse hack with the D f/f (probably). Which can be further simplified to one R-S f/f and a couple gates (the comparator gets hysteresis, to serve as the "slave" f/f in the master-slave D structure), but it's still kind of a lot of logic, or transistors, however you cut it.

Not very well optimized. Not very well engineered, you might say!

(Oh, and it's not shown with variable frequency, but the current sources are equal, so that is easily included, by anyone "skilled in the art" as they say.)

Tim

--
Seven Transistor Labs, LLC 
Electrical Engineering Consultation and Contract Design 
Website: http://seventransistorlabs.com
Reply to
Tim Williams

No, I think mine might work. At -ve Verr the outputs are tending to be in-phase, at 0v Verr the outputs are 50% out of phase (or 90deg phase shift if you prefer) and at +ve Verr the outputs are tending to be in anti-phase (or 180deg shift)?

I think because the flip flop divide-by-two applys to both channels the phase is preserved, or have I blundered?

Might have a go at analysis or LT Spice later.

Thanks for showing me your circuit, will need to study it.

piglet

Reply to
piglet

Seems so weird to see Freescale/Motorola parts on the NXP websiite !

boB

Reply to
boB

But that's so *LAZY* :)

--
Les Cargill
Reply to
Les Cargill

On a sunny day (Wed, 17 Feb 2016 20:38:13 -0600) it happened Les Cargill wrote in :

It is called 'efficiency'. :-)

Reply to
Jan Panteltje

It is called 'efficiency'. :-)

PS did you know PIC has 2 hardware comparators and a FF? I use those comparators a a lot.

Reply to
Jan Panteltje

Yes. We'd used one of them on some really small PIC16 for power/reset management of the main processor in a former life. Nicely boring, but the thing sure worked.

Wot's an FF?

I've trolled through this a bit:

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My favorites are the capacitive voltage doubler and the delta-sigma ADC.

--
Les Cargill
Reply to
Les Cargill

Dang! You are right Tim. I have blundered, my sketch does not cover the full 0-180deg range as I thought - another coffee-time wasted.

piglet

Reply to
piglet

On a sunny day (Thu, 18 Feb 2016 02:35:40 -0600) it happened Les Cargill wrote in :

Nice document. I never did the comparator delta-sigma in PIC, tried it on a FPGA input... then bought a real ADC for that. but I did voltage doubling by using a Villard circuit on the clock output pin (need to enable that).

Funny, they even give a comparator PWM example :-)

For a continuous variable frequency source the comparators can be used. PWM done in the internal hardware PWW generator.

But 'continuous' has little meaning without specifying the granularity, in a universe where physics claims Planck size etc Planck time ;-) So maybe using the counter controlled by an ADC that reads an input pin would give fine enough frequency control. For even finer you can defeat Planck ( :-) )by heating the chip to control the frequency.

There is an application note to use the watchdog oscillator as temp sensor, I did it here:

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I have used that comparator as analog TV sync separator, current limit detection via a current transformer for a MOSFET output stage, GM pulse detector, etc etc, basically everywhere where you need to 'immediately' switch something. The comparator allows you to terminate an ongoing PWM pulse in progress in hardware. Cool. And all the 4 phases are supported in that PIC module too.

Reply to
Jan Panteltje

On 18/02/2016 08:54, piglet wrote:

This one may work, uses one more stock comparator and op-amp but retains all timing derived from one ramp. It loses the guaranteed 50% duty cycle outputs. S-R flip-flop is a bit clunky but shows the principles, something edge triggered would be better?

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2 !.tran 1.5m TEXT 648 504 Left 2 ;Phase Shift Modulator TEXT 648 560 Left 2 ;EPW FEB 2016 TEXT 648 448 Left 2 ;SED Tim Williams Challenge

piglet

Reply to
piglet

That's a good one.

Crappy part is, a double-clocked F/F doesn't exist. Not that it's not possible, but nobody has one handy as a stand-alone chip, and no HDL synthesizer will allow it (naively, anyway). You can write one manually from the combinatorial parts, but that'll just synthesize to multiple LUTs with delay as bad as doing it discrete. (Discrete uses e.g. 8 x NOR, by the way.)

There's a phase detector that does this, but I don't think it's available in the *4046 flavors, not that you'd need the extra stuff that comes with, anyway.

Unless there's a way to use that stuff to your advantage...

Tim

--
Seven Transistor Labs, LLC 
Electrical Engineering Consultation and Contract Design 
Website: http://seventransistorlabs.com
Reply to
Tim Williams

Thanks, Tim.

I wonder if using two F/Fs, one for each edge would do ... hmm.

piglet

Reply to
piglet

That's the most commonly shown version of it -- but you still need an AND gate to reset them, and a third (RS at least) to hold the result.

I can't find a complete circuit (and damned if I knew the name, if the configuration even has a proper name), but it's a one of these

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with an R-S on the end, for obvious(?) reasons.

On an unrelated topic, this is neat I guess,

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Tim

--
Seven Transistor Labs, LLC 
Electrical Engineering Consultation and Contract Design 
Website: http://seventransistorlabs.com
Reply to
Tim Williams

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