DDR FPGA Design

Be realistic and don't let yourself fooled by succes stories. If you stay within the timing limits of the FPGA, you'll be just fine. And remember: there are no free DDR implementations available. So either roll your own or buy one.

Clocking the data from the memory is an issue if you use fpga's. Timing may vary a bit from device to device. The more layers of logic you add to the data input path, the bigger the variation in timing, the worse things get (this is why the MIG tool from Xilinx makes such a kludge of a DDR implementation). Use the flipflops in the IO cell to clock the data into the fpga. If you take all the timing variations and jitter into account, you can determine a window (with respect to the DDR clock) in which the data will be stable. The only thing you need is a (shifted) clock with an edge inside that window. If you can't get the window big enough, lower the frequency or use a faster fpga.

Is there a minimum transfer speed for ddr & ddr2 memories ..? Ie should you want to clock them at 10 MHz, then you can't etc..

Some memories can operate down to 83MHz. A Spartan 3 series speedgrade

DDR2 memories have a guaranteed bottom end of 125 MHz. In either case, the memory data sheet will show you the minimum frequency your memory device is specified for. If the chip uses a DLL to align the strobes, a minimum frequency spec is necessary.

- John_H