dac architecture

John Larkin wrote

Yes, but you can get more linear varicap effect by using for example 2. This paper shows some topologies and their effect:

Then use a linear opamp feedback loop?

I am using something like fig 1b on page 3 for my 25 MHz PLL reference for Eshail2.

A TCXO wouldn't need a very linear varactor, but a tight PLL does.

I have a new circuit that starts a 600 MHz coaxial ceramic resonator colpitts oscillator at trigger time, and phase locks it to an OCXO asap, still preserving the phase of the oscillator relative to the trigger. It uses an ADC to digitize the phase difference, an FPGA to do the math, and a DAC+varicap to tweak the CCRO. It also uses a dual varicap per fig 1b in your paper. Driving the varicap junction is interesting. I designed the loop and can barely understand it myself.

The TCXO thing I posted is interesting because it's delta-sigma in space instead of the usual delta-sigma in time.

John Larkin wrote

What I do not understand in your circuit is you say you are afraid of phase noise, and that is why no DAC. But this circuit also switches frequency abruptly, or is there some low pass?

Else a look up table before a DAC could give you any curve? In my tritium delay experiment I use the low pass filtered PWM output from a PIC, like this: diode temp sensor -> 10 bits ADC -> software -> 8bits (IIRC) PWM -> low-pass -> TO220 as heater. and can make any curve in software. All I care about there is some overshoot, experimentally found a good vale, been working for > 4 years now within a fraction of a degree C, or better within +- 1 ADC step :-)

There are a million ways I am sure... took half an hour to find the optimum values...

That circuit is conceptual, certainly not done. Only one comparator switches at a time, and each step would change the frequency PPBs. Sure, lowpass the varicap drive. Even better, make the comparator gains low so the transitions are soft.

A TCXO doesn't need a static-in-static-out lookup box, because termperature changes incrementally.

Is there a difference between building this circuit and adding an LPF, and using a traditional DAC and adding an LPF? Either way, you aren't going to add significant phase noise beyond the LPF cutoff.

A DAC-driven control loop can work well without a whole lot of head- scatching. (Almost) everyone with a GPSDO has one of those. Remember, TCXOs and OCXOs don't have a lot of kVCO gain, so they aren't that vulnerable to noise injection. At least not compared to microwave VCOs that run at 100 MHz/volt, and that are also often pretuned by DACs.

-- john, KE5FX

At a given frequency you can do a good job of linearizing a varactor by using one inductor in series, resonated just off the high-capacitance end, and one in parallel, resonated just off the low-capacitance end.

Cheers

Phil Hobbs

Couldn't you do it all digitally and then low pass filter the output so that the phase noise is kept within acceptable bounds. Sounds like you will need to calibrate every one against a good reference oscillator.

Looks pretty different to me. There's no clock to make power supply and varicap noise. Incremental linearity is almost perfect. Might be suitable for integration.

I just thought it was an interesting nonlinear function generator that I hadn't see before. Low integrator gains would be interesting too.

Any good TCXO will need to be temperature swept and calibrated. You can trim resistors in a thermistor network, trim polynomial terms, load a ROM lookup table, or flip my row of switches. The cal has to be nonvolatile somehow.

Most small TCXOs have a couple of DNC pins which I assume are an SPI-like programming port.

"NC" sometimes means "not connected internally" and sometimes means "do not connect to this pin."

John Larkin wrote

The old way I did things like that was also clock-less: ADC-8-bits -> address-EPROM-data -> DAC. Conversion table in EPROM [1]. There is then still some noise, as bits do not always appear on the EPROM output at the same time, there are time differences in address lookup, but 't works. For a wider bus use 2 EPROMS for 16 bits etc. [1] EPROMS were those chips with a little window where you could see the silly-con and give it a sun-tan to make it lose its memory. I still have some 2732 around somewhere and an UV tube.

Well... actually...the ones I am designing do.... :-)

The problem is compensation skew with control voltage. The compensation might be doing a 500:1 nullification. If the V-F is nonlinear, changing the control voltage, changes the compensation. 0.1% linear is a target.

There are two basic ways to linearize the transfer function. Linearizing the varacter or pre-distorting the drive voltage.

There are quite a few patents, going back to the 60s on connecting varacters with individual dc offsets to do this.

-- Kevin Aylward

Maybe you could use a standard xtal TCXO asic and use it just for its inbuilt nonvolatile DPOTS driving its polynomial compensation?

Its a standard problem, already solved for 20+ years.

We (Rakon) don't source our own asics to external customers, but AKM does

-- Kevin Aylward

Its also relative the speciation's that are actually required :-)

For xtal TCXOs, despite having say only 20ppm/V, which aint a lot, the limitation for close in phase noise (1Hz) may well be the compensation noise injected onto the varactor, not the oscillator noise.

-- Kevin Aylward

Sure, you can always buy a chip and an eval board and not design anything and be done. But then, all your competition can too, so it becomes a race to the bottom on volume and cost.

I just thought this architecture, delta-sigma in bit-set space, was interesting.

No public data sheet, apparently. How does that one work?

PS I would not even bother with a DAC. For tuning, fine tuning that is, an EPROM output with an R2R network as DAC for 256 steps should do, followed by a lowpass. If the EPROM logic output levels are not really CMOS Vss and Vdd, then use a CMOS buffer. Some resistors from the same batch. Clock, what clock? Done it for video with R2R on FPGA output, works great.

But a small cheap DAC is so tempting. I started with a PWM signal filtered with Stephen Woodward's trick, for my MPX-16H DAQ ** and finally realized an honest DAC made more sense, and updated the PCB to an MCP4921, a 12-bit DAC in an SOIC-8 package, only $1.50 qty100. ** MPX-16H bare boards, free, snipped-for-privacy@yahoo.com

On a sunny day (7 Jan 2019 09:23:44 -0800) it happened Winfield Hill wrote in :

Yes, sure, but that is a serial SPI input DAC that needs a clock, and a micro. he wants no clock?

The R2R, or if you are brave 8 resistors ratio 1,2,4,8,..128,

on the output of an EPROM data bus, well lemme draw something:

Resistors are cheap, leaves him more money for skying.

Flash ADCs are fast, not so many bits,,, like your 24 ! That is amazing.

I have never used a 'duino in my life ;-)

With season passes to Sugar Bowl and Tahoe Donner, incremental skiing is free. Well, I do have to pay for the mid-day rum+coke.

I was thinking of the weird dac as an IC in a TCXO, but generally just thinking of a physically linear delta-sigma thing.

It would be tough to make a real 8-bit DAC out of resistors and CMOS levels.

You might also sum a large number of bad (2 or 3 bit) DACs to get sort of the same effect I was considering.

There are some DACs that implement their three MSBs as 8 equally-weighted resistors.

Not sure if I understand correcty, but whenever there is a discrete level change, there will inevitably be some injection of phase noise. So what are you trying to avoid?

Best regards, Piotr