d-flop critical timing

Beautiful!

Cheers

Phil Hobbs

If some attention is paid to driving it, the inverted pendulum DOES rock back and forth. The typical demonstration uses a reciprocating saw to drive the pivot:

I'm told that this all makes sense, if you study Matthieu functions long enough. Like, probably about a week.

More to come.

This is interesting enough that we can put another day or so into it. The test is automated, so we can kick it off and do something else.

It would be fun to test the flop itself, without jitter contributions from the comparators and things, but that would be over the top.

Samsung has patented what they claim is a novel form of ECL D-type bistable.

Figure 11 seems to be the circuit diagram

One could simulate it in Spice using something like the BFR92 wide-band transistor for all the transistors shown.

It's questionable if the ringing on the output should be described as an "oscillation". An exponential decay with an imaginary part will show a sinusoidal but decaying component - perfectly determinate, but with quite a bit of visible structure.

My guess would be the that LSTTL had decided which way to resolve before it started ringing and that sufficiently careful examination of the first cycle would show which way that was.

Even if that it true, it is not especially relevant. The fact that the oscillation is simply on top of the "deterministic" movement to one result or the other is not the issue. What is significant is if the final state can be determined by the value of the input at the "sampling time". Certainly for a wide range of inputs the output will be known and monotonic. But looking at JL's data I see regions of chaotic behavior if I am interpreting it correctly. The rising edge of the data is over a very small percentage of the chart, so it is hard to see just what patterns form. But it looks like there are a number of regions where the behavior is *very* much not monotonic.

Fortunately this is not important to what JL is doing. He is trying to measure jitter in a signal to a wider degree than the entire rising edge of the data in the graph, so the variations caused by the monotonicities will not be important.

e parts - and could tell John what he wants to know.

y.

n "oscillation". An exponential decay with an imaginary part will show a si nusoidal but decaying component - perfectly determinate, but with quite a b it of visible structure.

e it started ringing and that sufficiently careful examination of the firs t cycle would show which way that was.

It's not "on top of" but rather part of the deterministic moverment.

As usual, John hasn't spelled out exactly what he is posting. There does ap pear to be a sine wave running up the rising edge. If his sampling system i s looking at deterministic output with a decaying sinusoidal component (non

-monotonic) shortly after the active clock edge hits the output, this doesn 't have to be chaotic (which doesn't mean random, but actually determinate but hard to predict).

Monotonic is nice, when you can get it, but a predictably decaying sinusoid might be good enough.

Pere

I believe that is the definition of chaotic. Chaotic systems are not indeterminate, they are simply very sensitive to initial conditions which means a small perturbation can give rise to very different results.

I think we are talking about two different things.

The last behaviour is what I would expect. And I guess that saturation should come into play when the signal gets "big enough". The oscillations that you describe should be the consequence of a small signal second order dynamics and I can't see how they arise. The negative resistance associated to the cross-coupled pair together with parasitic capacitance give a first order term. To get complex poles you need something more going on. Do you have a link to real measurements as you were describing?

A FF is basically two series-connected gates with feedback from the last back to the first. If the bandwidth (think transition time) is fast as compared to the propagation delay, the thing can oscillate for a while, until asymmetries favour one fixed level over another.

Jeroen Belleman

I observed the oscillation some decades ago, when we still designed with LS.

The TI data sheet shows the transistor-level schematic. There enough doodads to make it a little complex.

Right. But when you draw it out, this becomes just a cross-coupled pair (just discussing the bistable part). And, in theory, there could be transmission line effects leading to ringing. I have even built some oscillators with discrete (and fast) transistors based on this, BUT with a length of transmission line (or one or two inductors). But this happens inside an IC, with both transistors *very* close! An when making integrated CMOS oscillators in the GHz range, big spiral inductors have to be included. This is not being done for fun -they take up a significant amount of chip area.

Again, while I won't argue against experimental evidence of oscillations, it still seems unclear to me how a second order behavior happens here.

Pere

Here's the final data on the NB7V52 CML flipflop:

The effective sampling jitter is around 50 fs RMS, which includes the jitter of the flop under test and the two ADCMP582 comparators that drive the differential clock and D inputs.

I think the data sampling time is around 16 ps before the clock, but that's hard to measure so may not be right. Call that "zero".

The tempco of Tsamp is nearly zero between 40 and 60C, which is around where we'll use it.