d-flop critical timing

Didn't say it would but why bother, then?

OK, that's the usual excuse. It can't be avoided, but the probabilities can be made tolerably low.

...or reading what people have actually written.

Reply to
krw
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How is that different from any continuous electrical measurement?

So we shouldn't bother to make the measurement?

More struggling to find reasons to not attempt anything new, to not even make the measurement.

The Tek 11801 sampling heads, the SD series, have horrible time shifts over ambient temperature. You can put your hand one one and see it drift picoseconds. I expect we'll be better than that.

Violating setup/hold timing will destroy the chip? We'd better forget the whole thing.

What's the name? Got a link?

We want to measure the jitter of a DUT-generated delay as a function of delay. It doesn't need to be stable for weeks. We don't even need to calibrate out any absolute time shifts, although we could.

At the picosecond level, cables and PCB traces will add a lot of delay tempco, no matter what test gear we use. The DUT is complex so will have its own delay tempco, many times what I expect from the flop itself. That won't much affect a jitter measurement that takes a couple of seconds to complete. Long delays, with multiple shots and a time sweep, could take many minutes to characterize jitter, but that would be a problem with any test gear. The telecom industry defines "jitter" and "wander" as distinct measurements, with the boundary being 0.1 seconds of measurement. Same issue, slow drift on top of fast jitter.

I can think of ways to cheat.

Will it be exactly the same?

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John Larkin         Highland Technology, Inc 

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Reply to
John Larkin

t
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more like what ever they do it'll (usually) resolve itself in such a short time you are unlikely to see it

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Reply to
Lasse Langwadt Christensen

There is nothing new here. The idea that you are designing an experiment that specifically selects the meta-stability region for its measurement and will only see 1 in 1000 meta stable events is a bit naive I think. But then I don't know anything about your numbers. If you are sweeping your 1 million measurements over a delay of several nanoseconds, then yes, a meta-stable event may be very infrequent. I had the impression you would be looking for jitter in a very narrow range of time which would make meta-stability much more frequent.

In your favor is a number on some FPGAs where the measured (or more accurately - calculated) window width was in the 10s of femtoseconds I seem to recall.

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Rick C
Reply to
rickman

What he meant was the settling delay was so short it would not be easily observed given even a single nanosecond of settling time. He was not saying it would not happen. The impact of meta-stability in a circuit is always a function of the settling time and an exponential function at that.

I have pointed this out in more recent discussions in c.a.f and been told newer devices have shifted back the other way.

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Rick C
Reply to
rickman

You haven't given any details of how you expect your circuit to work or what the time ranges are, but the potential problem with this is that even the probability of the output landing in a given state may not be a linear function of the setup time inside the meta-stable window.

I have no idea why you feel an oscillation will somehow "contribute" to your measurement. It will create an unknown contribution which very possibly will vary with uncontrolled factors.

The devil is in the details and the device you are working with may be well behaved. There are so many factors (including the details of your design you have not explained) that only testing will tell.

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Rick C
Reply to
rickman

This problem can exist in Verilog as well. VHDL uses delta delays to resolve this sort of problem.

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Rick C
Reply to
rickman

If the rest of your circuit is stable and relatively noise free, expect a window of 10's of femtoseconds. But allow for this window to *move*.

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Rick C
Reply to
rickman

[SNIP!]

That's when the output is both high and low at the same time, until you look at it, by which time all the uncertainty will have been magically collected into one single result, which may be one or the other. ;-)

Jeroen Belleman

Reply to
Jeroen Belleman

Why are you being this way? No one is saying you can't or shouldn't do this. Don is simply pointing out potential limitations you may find when you make the measurement.

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Rick C
Reply to
rickman

On Dec 3, 2016, John Larkin wrote (in article):

Yes. There is a huge literature. The best paper on the physics mechanism that I know of is "Theoretical and Experimental Behavior of Synchronizers Operating in the Metastable Region?, G.R. Couranz and D.F. Wann, IEEE Transactions on Computers, Volume: C-24,Issue: 6, June 1975, pages 604-616.

George Couranz was a colleague of mine.

Joe Gwinn

Reply to
Joseph Gwinn

But the metastable behaviour can be quite orderly - at least for some parts - and could tell John what he wants to know.

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Bill Sloman, Sydney
Reply to
bill.sloman

I haven't seen that response. The aperture time will drift around a bit, but not a lot, and probably not enough to prevent you using it to quantity your trigger jitter (though there's no way of guaranteeing that).

That's krw.

Tinkerer warning, if the measurements are yours.

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Bill Sloman, Sydney
Reply to
bill.sloman

It might be interesting if you could also measure it on the ADI comparators ADCMP572 / 582 etc. which have a latch input and so could be used in place of your D-ff.

You could sweep the latch and input edges slowly past each other, and for each time offset gather a percentage of high vs low outputs (as I think was your intention).

You could also sweep the edges slowly past each other, and for each time offset, search for the voltage applied to the other comparator input by a DAC, which will result in 50% high outputs. This should form a very slow sampling DSO, in effect.

A guy (Darwin Sabanovic) was offering something like this on Kickstarter a while ago, as I mentioned to you in Feb 2014:

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He said that the Hittite latched comparators were what he used, and had better bandwidth than ADI ones.

I had also considered building such a thing, but I was not intending to add external trigger as my uses were more similar to yours. I ws going to get two identical low noise voltage controlled crystal oscillators (VCXOs) (somewhere between 10 to 150MHz, maybe 26MHz ones from phones), and a ~ 2GHz VCO. I would make one of the VCXOs fixed (or locked to the lab 10MHz reference), and then lock the microwave VCO to the first VCXO with a frac-N PLL, and lock the second VCXO to the microwave VCO with a second frac-N PLL - (this PLL being used in the reverse of the usual fashion, i.e. the crystal oscillator being tuned and the higher frequency input being at a fixed frequency from the microwave VCO). I would choose slightly different numerator and denominator settings for the two frac-N PLLs so that the two crystal oscillators would drift slowly past each other at maybe 1Hz. By using frac-N PLLs, the PLL bandwidth can still be very wide so that the close-in phase noise of the VCXOs (and VCO) is removed and they both have the (same) close-in noise from the lab reference. This correcation in the jitter should be helpful.

The above scheme should allow one to sweep the edges of two signals past each other with very low relative jitter. Of course some serious shielding, supply filtering, and output buffering to separate the VCXOs would be needed to stop them tending to injection lock.

Chris

Reply to
Chris Jones

Yes, a strobed comparator would do about the same thing.

The 582 has random jitter of 200 fs typ. That spec doesn't involve the strobe input but it's in the speed ballpark thet we want.

The latch setup and hold times are "typ" 30 and -25 ps, whatever that means.

Yes, but in real life the sweep would be discrete time steps. About the same thing. We could do just a few measurements to get a pass/fail jitter test on the DUT without plotting the entire integrated-probability-distribution curve.

That would make a 1-bit tracking sampling oscilloscope with around 8 GHz bandwidth.

That's cool. That could also be done with a differential EXL flipflop, instead of a comparator. NB7V52 is faster than the '582 and half the price.

He should have my deconvolution algorithm, too!

I'm guessing that would have more jitter than a conventional ramp-comparator timebase, which could also be triggered.

We did test the eval board for the TI LMX2571 synthesizer. Short-term jitter, 1 to 10 cycles or so, indicated 1 ps RMS, which is the noise floor of the scope we used. That's an amazing chip; it would have been a rack full of gear 25 years ago. Two of those, clocked by one common XO, could do your delta-F time base.

I recently built a TDR based on this 1-bit sampler idea. Haven't had time to test it yet, and I don't really have a use for it. Just for fun, so far.

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SD24's are cheap on ebay!

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John Larkin         Highland Technology, Inc 

lunatic fringe electronics
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Reply to
John Larkin

Yes, a strobed comparator would do about the same thing.

The 582 has random jitter of 200 fs typ. That spec doesn't involve the strobe input but it's in the speed ballpark thet we want.

The latch setup and hold times are "typ" 30 and -25 ps, whatever that means.

Yes, but in real life the sweep would be discrete time steps. About the same thing. We could do just a few measurements to get a pass/fail jitter test on the DUT without plotting the entire integrated-probability-distribution curve.

That would make a 1-bit tracking sampling oscilloscope with around 8 GHz bandwidth.

That's cool. That could also be done with a differential EXL flipflop, instead of a comparator. NB7V52 is faster than the '582 and half the price.

He should have my deconvolution algorithm, too!

I'm guessing that would have more jitter than a conventional ramp-comparator timebase, which could also be triggered.

We did test the eval board for the TI LMX2571 synthesizer. Short-term jitter, 1 to 10 cycles or so, indicated 1 ps RMS, which is the noise floor of the scope we used. That's an amazing chip; it would have been a rack full of gear 25 years ago. Two of those, clocked by one common XO, could do your delta-F time base.

I recently built a TDR based on this 1-bit sampler idea. Haven't had time to test it yet, and I don't really have a use for it. Just for fun, so far.

formatting link

SD24's are cheap on ebay!

--
John Larkin         Highland Technology, Inc 

lunatic fringe electronics
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Reply to
John Larkin

Metastability is a deterministic beast -just the effect of instability. A regenerative comparator is just a negative resistance making a first order circuit unstable. If anybody likes some fun, have a look at

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Pere

Reply to
o pere o

Metastability in a flipflop, especially a symmetric master-slave flop, is complicated by saturation. It doesn't behave like an inverted pendulum. The inverted pendulum eventually falls one way or the other, but it doesn't rock back and forth first.

LSTTL could oscillate for tens of cycles before deciding which way to resolve. ECL sometimes oscillates before resolving. Transmission-gate cmos is more likely to behave like the linear models... hang at some intermediate output level, then snap to a rail.

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John Larkin         Highland Technology, Inc 

lunatic fringe electronics
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Reply to
John Larkin

I found this on my desk this morning:

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Looks like around 150 fs RMS jitter, which includes the flop and contributions from the test circuit and such. Tsamp seems to be about

-16 ps, which is the actual "0" on the x-axis. 16 ps is essentially zero anyhow.

This took about 15 minutes, so there is some temperature drift included. We'll run an overnight test too.

--
John Larkin         Highland Technology, Inc 
picosecond timing   precision measurement  
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Reply to
John Larkin

Is it now time to change your company tagline from Picosecond engineering to Femtosecond engineering ? :)

piglet

Reply to
piglet

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