d-flop critical timing

Nice stuff. I have used an ecl dflop as the phase detector in a 155.52 MHz PLL, the NIF timing system, where time stability was important but the loop filtering hid jitter and metastability.

We're trying that. It's not simple to generate the swept delay; we may well wind up measuring the jitter of the test circuit more than the jitter of the flop.

Right. If it's good enough, we sort of don't care what is the dominant noise source. If we can measure below 1 ps RMS jitter, that will do, but I'd like it to be better, for future use.

Yeah, averaging a lot of shots, especially for long delays, takes real time so gets us into thermal 1/f noise and such. Differential ECL is pretty good, somewhere below 1 ps/degC, but I think we should try to measure that too.

--

John Larkin         Highland Technology, Inc 

lunatic fringe electronics

Right. I had to edit the flop model to add some prop delay.

--

John Larkin         Highland Technology, Inc 

lunatic fringe electronics

I suppose you could generate the delay mechanically, like a motorized trombone line, or more prosaically sliding a chip along a pcb trace :)

piglet

Am 03.12.2016 um 19:02 schrieb John Larkin:

In ADCs this is called aperture delay, and it can be positive or negative. Its variation is called aperture jitter, in typical

100 MSPS 16 bit ADC it is 65 fs, usually in the data sheet and probably just what it takes to make a 16 bit 100MSPS ADC.

So you could probably just fit a curve through some samples.

regards, Gerhard

Why so hard? You can use a trombone variable delay line, a series LC or RC with a variable cap, or simply adjust the threshold voltage on one differential clock input while applying the clock pulse to the other. If you know the risetime, you know the delay.

I'm not so sure about the RC delay noise, but if you keep the R very low, such as 10 or 25 ohms, it should have little additive noise compared to the d-flop. LTspice will give you noise measurements to compare the RC and LC delays.

I have actually tried to make these measurements several decades ago, using an EP52. I found it impossible to induce any metastability in the ECLinPS devices whatsoever, and the transition width was below my capability to measure.

It was essentially zero, which corresponds to the 26 ps mentioned in the articles posted above. Note this not include the device output jitter, which is a completely different thing.

Am 03.12.2016 um 21:35 schrieb Steve Wilson:

On a XFEST quite a few years ago I heard Mr. Alfke say that metastability was a non-issue for the then-modern FPGAs (Virtex4..) Multi-stage synchronizers would make no sense at all because of the extremly short loop delays of the flipflops.

Peter Alfke used to write most Xilinx app notes, he should be retired by now.

regards, Gerhard.

ann:

I may well be misunderstanding you, but halfway is neither high nor low.

If I didn't respect your circuit design chops I'd suggest you call it T_stupid, as a hint about the wisdom of trusting it outside of a temperature controlled lab with just one gate on just one part.

Instead, I'm going to ask -- what are you _really_ trying to do? Normally if I needed to push this parameter for some reason, the first thing I'd think to try would be a faster logic family, or a rearrangement of the circuit to just keep the situation from being a problem.

--
Tim Wescott 
Control systems, embedded software and circuit design 
I'm looking for work!  See my website if you're interested 
http://www.wescottdesign.com

One could move a dielectric above or along a microstrip, or heat the board to change prop delay. We did it electronically with comparators, so part of the jitter that we measure will be the parts in the test circuit.

Varicaps could be used along a txline to make a very low jitter time modulator.

--

John Larkin         Highland Technology, Inc 

lunatic fringe electronics

Peter died a few years ago. I first met him at the Foothill Electronic Flea Market, when we found both our heads inside a big box of old books. He was a great guy.

--

John Larkin         Highland Technology, Inc 

lunatic fringe electronics

Peter Alfke died some years ago.

I met him once.

(Those two statements are not related.)

Allan

One gate should be a lot more stable than an oscilloscope full of amps and ADCs and yet more gates. Our best scope has 1 ps RMS jitter, and that's for short delays between trigger and measured edge.

We want to test a laser driver that includes a programmable delay generator. We want to characterize jitter vs programmed delay. This will be a production test, and we'll build at least two test sets, and we don't want to dedicate a couple hundred K$ in equipment.

The idea is to have a really good OCXO in our test set. Through one path, it triggers the DUT, usually dividing down the trigger rate. The delayed DUT output clocks a d-flop. The OCXO square wave is the D input of that flop. As we slowly sweep the delay generator, we will see the flop Q output go up and down with an equivalent-time period equal to the OCXO period. Once we find an edge, we can make tiny time delay tweaks in the vicinity of the transition, and measure both the time of the edge and the jitter. We can derive a jitter-vs-delay curve that is as good as the OCXO.

A really good OCXO will have fs period jitter, and longterm jitter of a few ps per second.

--

John Larkin         Highland Technology, Inc 

lunatic fringe electronics

Over thousands of trials, adjust the time between the D and clock rising edges until Q averages 50% high. Note that time.

Then sweep the time a bit around that point and plot the averaged Q level vs delta-T.

--

John Larkin         Highland Technology, Inc 

lunatic fringe electronics

Many moons ago, I modulated the current in a current switch (AKA ECL gate) for fine delay adjustment.

Right, but these are the guaranteed values across the process. Each flop also has its specific value(s).

There is a critical (dead) zone between the two (if you can find it). The two numbers still exist. Sure it's statistical. The closer you get to the edge, from either direction, the higher probability of metasability.

I'd expect it to be dependent on the environment (temperature and VCC), too. It's all a matter of degree.

The "terrible thing" that happens is meta-stability - the logic output is s omewhere between 0 and 1. Unless you hit the meta-stable point exactly righ t, the output will be moving towards 0 or 1 progressively faster.

If you look at the logic output with an analog sampling scope the actual vo ltage level at time when you sample the output will given you fine-grained information about where the aperture point actually is, subject to the poin t that it isn't going to be all that stable, since it's going to depend on thermal and electrical stuff going on inside the chip.

And the internal noise of the D-type flip-flop. Make the bistable the faste st ECl part you can lay hands on and you minimise the internal noise.

Why would they bother? The whole point about metastability is that you want to avoid it.

This is nonsense - the Q has to change state for you to measure anything, a nd the change from 1 to 0 is going to work differently from the change from 0 to 1.

You've got two different aperture points for two different transitions.

If you leave the Q output in a 1 state for any length of time the heat dist ribution within the chip is going to be different from the one you see if y ou leave it in the 0 state most of the time.

--
Bill Sloman, Sydney

You have a good name now: Tcr", along with a good definition.

But when you hit the metastable point, the output will be neither high nor low. So the answer to the question "is Q high 50% of the time" can only be "mu"

Or are you assuming that there will be sufficient uncertainty in the sampling instant that the chance of hitting the metastable state is negligible?