Current Mirror Conundrum

I am the EE equivalent of Professor Kingsfield... show your work ;-) ...Jim Thompson

Rout = RO*(1+GM*(RE||RPI)

Assuming you are going RO*(GM*RE), I get the same number. That neglects RPI.

Do you have some sort of headroom issue? You could add two more BJTs and just brick wall it with a cascode.

RPI would be about 5k at 10ma. It would show up in the math, but you have a factor of 10 over RE, so it wouldn't make much difference.

I could use a cascode -- that's not a bad idea -- but I'd hate to take a shot in the dark and miss. The board is already laid out and fabbed, I was just dotting 'i's and crossing 't's before I did the turn from proto to production. I did _not_ expect this problem!!

I _really_ want to know what's up before I proceed.

=3D

Have you figured in the Early effect, aka base-width modulation with changing collector voltage?

The Gummel-Poon model includes this effect - albeit rather crudely - so you'd see it in an LTSpice model.

As miso says, adding a cascode transistor reduces the problem a lot. It's a well-known option.

-- Bill Sloman, Nijmegen

I did a datasheet search for the BJT and one of them had the H parameters versus Ic charts. The Early effect is taken into account in my calculations since it is in the H parameters. The OPs back of the envelop calculations looked good to me.

I've only done these ratioed mirrors with true ratios. No big deal on a chip. Just plop down more transistor, perhaps with the unit transistor surround by the array if you want to get fancy. Operating the BJTs at different collector current should introduce some error, but it shouldn't be that significant.

With the board already designed, that leaves component changes. If the problem is related to the ratios, burn more current on the reference side (decrease the ratio). Increase the resistor to drop more voltage, making Vbe less significant, at the expense of headroom. Use a different transistor, small signal instead of switching.

Lastly, this scheme does have a potential for supply noise to modulate the current. When it comes right down to it, you really only have a voltage reference in circuit design. For an accurate current reference, it should be derived from a voltage reference. I've used that "peaking" reference in situations, but it is really inaccurate. However, if you need a current source at low voltages without all the hassles of V to I, it is worth considering.

Looks as good as any paper on the net on the topic. I think the circuit is out of Gray and Meyer.

How do you measure the the 200us? DC or AC?

Think about power dissipation... it isn't something to neglect.

Say you test DC with dV = 1V.

All that leads to roughly 10mV/(49.9+1/(0.038*10)) = 190uA collector current increase, which is very near your measured 200uS output conductance...

Measure it at 10kHz and it'll be what you calculated...

Cascoding could be a good solution. Or the Wilson or improved Wilson (with 4 Qs) current mirrors will work nicely too.

=3D

Who could possibly answer that question without any information regarding compliance and accuracy required?

How did you measure it? DC or AC ? Miller effect?

Vladimir Vassilevsky DSP and Mixed Signal Design Consultant

That would not only explain things, but it would save my butt -- I did the measurement at DC, and I did note some lag ("dang", I thought: "what process would have a one or two second settling time?"). The measurement itself is a few short pulses that are over in about 1/10th of a second, so any temperature change they cause may well come in under the radar.

I'll check that if I have the chance (I'm meeting with the customer in about on hour and a half), or at least I'll have an excuse to babble at him.

Yes -- the output impedance of the transistor alone, from Early effect, is 5k. With the emitter degeneration resistor it's more like 100-200k.

Anyone who read the "it is A, it should be B, help me figure out why".

DC. See my response to Mr. Bartoli, who may well have nailed it.

Well...you DO get about 10mA, nicht var?

=3D=3D

t'll

But it is not an impedance issue, it is a drift problem.

=3D

This won't budge a bit:

Please view in a fixed-width font such as Courier.

. . . . +18V . | . .----+----. . | | . | | . |LM385 [120] . ----- | . | + |FB | . | |------+ . | - | | . ----- | . | |< . +-------| 3906 . | |\ . | | . [15K] | . | V . | . --- . /// . . The trick is to use a single LM385 for multiple sources :-) The obvious arrangement doesn't work very well.

What I need is an output impedance over 100k-ohm from 0V up to about

Basically 2.2mv/deg C *4 deg C change (Kelvin is just an offset) =

The 4 transistor scheme is less sensitive to base current error. But putting those extra BJTs on the output side would reduce the VBE shift and make the current ratio more accurate.

Or a package with better theta ja. To some degree you can cheat by adding more copper to the output side device since much heat is carried by the bond wires.

Or a customer that says "oh, as long as the time constant is over a second, that's fine". That's a great solution, too :D.

That leaves you with only about 2V to play with... not a lot, but try the cascoded versions, but with R in the emitters.

A quick and dirty throw-together yields 17.8uS for a Wilson-type, and