Current leak in Opto-isolator

ses a Vishay VO14642AT Solid State Relay to connect and disconnect an exter nal battery to the main circuit. See the link below. The off-state leakag e current of this device is supposed to be less than 1 microampere, but whe n the device is inserted into the circuit with no bias on the LED, the devi ce is passing about 3ma with a 500mv drop across the output terminal when 9 V DC is applied. It is enough so the DC-DC converter on the output of the isolator is producing a full 5V out with no load. What am I doing wrong? When the isolator is removed, the voltage drops to zero, so the leak does n ot appear to be anywhere else in the circuit.

He paralleled the internal FETs for increased current capability. And altho ugh the datasheet clearly states the common source connection is the "negat ive" output, he connected to the most positive node and lost turn off contr ol.

"Design"? ROTFLMAO >:-}

What is your "CADD" program, "Paint"?

Rotten symbology. What is that abortion to the right of designator Q6? An OpAmp with no power pins?

And you left out some of the pins (and numbering) for O1... critical to your failure.

Q4 can leak like a sieve... SW2 doesn't really do squat.

Plonk.

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I do my best to assist amateurs in understanding Analog Circuit Design and Spice Modeling, but when they're totally incompetent, and snarky to boot, I am under no obligation to continue.

This thread is herewith abandoned.

Students and engineers wishing details, derivations, etc., should go to my website...

and utilize the envelope icon to request technical information.

All requests are cordially invited, though requests for help with homework assignments will most likely be ignored >:-}

I also invite you to partake of the LTspice list, where true technical discourse still exists.

...Jim Thompson

hough the datasheet clearly states the common source connection is the "neg ative" output, he connected to the most positive node and lost turn off con trol.

Are you saying you have never accidentally wired something backwards, despi te knowing perfectly well how it should be wired? I made a wiring mistake. It happens. It's also why I didn't catch the error at first. I was thin king there was an issue with my design. Geez.

lthough the datasheet clearly states the common source connection is the "n egative" output, he connected to the most positive node and lost turn off c ontrol.

pite knowing perfectly well how it should be wired? I made a wiring mistak e. It happens. It's also why I didn't catch the error at first. I was th inking there was an issue with my design. Geez.

If you want to hang out here and interact, you need to develop a thick skin. We're all experts on everything and never make mistakes. :^)

George H.

This is what you call appropriate discourse? What are you, 12 years old?

Not program. Programs. AutoCAD, Visio Pro, Libre Office draw. For this I just used Visio. How is that relevant to anything?

An incomplete drawing. I haven't finished the design, yet. How is that re levant? Is it necessary to the section with which I was having problems? No. Does it impact troubleshooting this issue? No.

Irrelevant to my failure. It was not a design issue. Had I added the numb ers, at best it would have done nothing to point out the problem. At worst it might have prevented Lasse with coming up with the correct answer. Aft er all, the design called for D3 to be connected to pins 4 and 6 of O1 and for the collector of Q4 to be tied to pin 5.

You're kidding, right? I am starting to think you don't even know how a tr ansistor works. SW2 works perfectly to shut down the DC-DC converter. Sho rting the base of Q5 to the collector of Q4 completely removes all charge f lux through the base of Q4, which causes the potential at the emitter of Q4 to fall to zero, shutting down the RPi. Don't try to tell anyone it doesn 't either. I can provide a video of it working perfectly.

Whether or not you think Q4 can leak like a sieve, it doesn't in fact, per design. Even if it did leak a little, which it doesn't, it would not hurt. As long as the output voltage of the DC converter falls momentarily below 4 V when SW2 is pressed, it is doing its job.

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If this is your best, I would truly dread seeing your worst. Yo have added nothing, ABSOLUTELY NOTHING to the discussion here. Arbitrary criticism, especially of irrelevant and trivial issues is never helpful.

Ad hominem attacks are prurient and childish.

I'm snarky. Right. And incompetent. Uh-huh. I agree you are under no ob ligation to continue. Not only are you not required to do so, you are not requested to do so. Removing all of your posts would not impact the discus sion in any negative way.

although the datasheet clearly states the common source connection is the "negative" output, he connected to the most positive node and lost turn off control.

espite knowing perfectly well how it should be wired? I made a wiring mist ake. It happens. It's also why I didn't catch the error at first. I was thinking there was an issue with my design. Geez.

on the other hand getting all fired up if someone suggest otherwise fits right in ;)

te:

ainly through the 12V supply and Q4.

in saying the 9.6V battery is the only source of power at this point in te sting. I don't see how Q4 could be a culprit in any case. If +12V is on i ts input, then it will be fully saturated by design, not leaking. If not, then I fail to see how leakage through Q4 would bias O1's LED.

LED current is derived from the 5V DC-DC output???

booted the computer and the RPi has asserted GPIO 19 in software. Once do ne, the circuit has latched the SSSR through the RPi. If +12V fails, then by the fact the battery is feeding the input of the DC-DC converter, +5V re mains intact, and the computer remains active, despite having presumably lo st AC power. GPIO 17 informs the computer of the loss of mains power, and at a later time it will affect its shutdown procedure. When the computer s huts down, GPIO 19 is de-asserted, O1 is deactivated, and the battery is is olated from everything.

t most applications use a bleeder resistor across the SSR diode input. Sele ct R for half minimum diode VF at minimum turn-off current, or about 0.5V a t 50uA , making it 10kR across pins 1 & 2. I don't see a leakage source of that magnitude anywhere in your circuit though. Failing that substitute a n ew opto, but test it for basic ON/OFF operation on a plug board first.

't leakage it was the bodydiode

Quite easily. One grabs the trace one has designed to connect to the posit ive terminal and inadvertently connects it to the negative terminal. With multi-layer boards it is extremely easy to swap traces. In fact, I previous ly did so with another component on the board. I mounted a transistor (not shown here) on the bottom of the board. I thought I had flipped it, but I hadn't, so I wound up swapping the collector and base. Of course, when fi ring up the board, it was immediately obvious what had happened. This was a trifle more subtle.

His mental age is worsenning by the day.

He thinks app authors do not know how to strike lines, unless it is the app he chose to do so with.

He left that behind when he decided to start jabbing at you.

I wish I was as well spoken as you when I am a bit mift. There are a few folks in here I would succinctly place inti the fecal vat they belong in.

Jim Thompson is purient and childish. His IQ is based on it.

Good job. +1 on the post impact assessment!

Whopp that old 'snarky' bat's turd right upside da haed!

rote:

rtainly through the 12V supply and Q4.

er in saying the 9.6V battery is the only source of power at this point in testing. I don't see how Q4 could be a culprit in any case. If +12V is on its input, then it will be fully saturated by design, not leaking. If not , then I fail to see how leakage through Q4 would bias O1's LED.

ut LED current is derived from the 5V DC-DC output???

as booted the computer and the RPi has asserted GPIO 19 in software. Once done, the circuit has latched the SSSR through the RPi. If +12V fails, the n by the fact the battery is feeding the input of the DC-DC converter, +5V remains intact, and the computer remains active, despite having presumably lost AC power. GPIO 17 informs the computer of the loss of mains power, an d at a later time it will affect its shutdown procedure. When the computer shuts down, GPIO 19 is de-asserted, O1 is deactivated, and the battery is isolated from everything.

but most applications use a bleeder resistor across the SSR diode input. Se lect R for half minimum diode VF at minimum turn-off current, or about 0.5V at 50uA , making it 10kR across pins 1 & 2. I don't see a leakage source o f that magnitude anywhere in your circuit though. Failing that substitute a new opto, but test it for basic ON/OFF operation on a plug board first.

sn't leakage it was the bodydiode

itive terminal and inadvertently connects it to the negative terminal. Wit h multi-layer boards it is extremely easy to swap traces. In fact, I previo usly did so with another component on the board. I mounted a transistor (n ot shown here) on the bottom of the board. I thought I had flipped it, but I hadn't, so I wound up swapping the collector and base. Of course, when firing up the board, it was immediately obvious what had happened. This wa s a trifle more subtle.

Okay, dunno if you're using actual circuit board design software, but they all have DRC (design rule checking) that makes mistakes like that impossibl e to go undetected. DRC also verifies that board layout IS the schematic en tered.

Well, thank you for the kind words and the support. I suppose working for more than 40 years as an engineer has its up side. Honestly, though, this isn't relevant, either. I am highly tolerant of anyone who has anything ev en remotely topical or helpful to say or an intelligent question to ask. I have almost infinitesimal tolerance for any unhelpful, trivial, irrelevant , or incorrect remarks and none whatsoever for personal attacks.

So while I am truly grateful for your kindness, please let's move away from any discussion about any person and stick to talking about electronics. OK ?

If it was actually a "CADD" program, pins numbered, and netlist generated and simulated, I doubt that a visit here would have ever been necessary. Sheeeesh! Everyone can "afford" LTspice. ...Jim Thompson

y all have DRC (design rule checking) that makes mistakes like that impossi ble to go undetected. DRC also verifies that board layout IS the schematic entered.

I am, and it does, but trust me, it is not difficult at all. I'm using Fre ePCB. It's buggy and creaky, but it works, and of course I do employ DRC. However, just as a spelling checker will not catch the phrase "doe snot" i s supposed to be "does not", a DRC cannot know one has assigned a pin to th e wrong net, which is precisely what I did in this case. It only can asser t one has attempted to attach a pin to a net of which it is not a part.

I am not sure why I am bothering, but yes, CADD is the proper term. The last 2 or 3 decades it has become popular to shorten the term to CAD, largely one supposes due to the advent of AutoCAD, but the term is: "Compu ter Aided Design And Drafting". CADD.

It doesn't have a simulator. Otherwise, you doubt wrong.

hey all have DRC (design rule checking) that makes mistakes like that impos sible to go undetected. DRC also verifies that board layout IS the schemati c entered.

reePCB. It's buggy and creaky, but it works, and of course I do employ DRC . However, just as a spelling checker will not catch the phrase "doe snot" is supposed to be "does not", a DRC cannot know one has assigned a pin to the wrong net, which is precisely what I did in this case. It only can ass ert one has attempted to attach a pin to a net of which it is not a part.

It does catch that kind of error if it has schematic entry, but I guess you rs doesn't.

Visio is a loser all the way around...

Can't netlist, thus can't even do simple connectivity verification.

Can't be simulated.

Can't "talk" to PCB software.

The only good use I can see for Visio is generating "pretty" flowcharts... I find that useful in planning executables. ...Jim Thompson

they all have DRC (design rule checking) that makes mistakes like that imp ossible to go undetected. DRC also verifies that board layout IS the schema tic entered.

FreePCB. It's buggy and creaky, but it works, and of course I do employ D RC. However, just as a spelling checker will not catch the phrase "doe sno t" is supposed to be "does not", a DRC cannot know one has assigned a pin t o the wrong net, which is precisely what I did in this case. It only can a ssert one has attempted to attach a pin to a net of which it is not a part.

ours doesn't.

depends on whether the error was in the schematic

Hypothetically it's impossible to say fron that input.

You can look at the layout and try to figure it out from there.

eg: wires going to ground don't usually cross other wires, and wires near bridge rectifiers don't usually short out one of the diodes.

I think you missed the point. The dots aren't hard to see. The problem is that junctions should not cross at all. For example, you should have a horizontal line with two vertical lines that join it at different points. Then there is never any ambiguity, and no chance that an error would happen because a dot was left out or mistakenly put in.

That has been the drafting convention since the 1970's.

There are times when this will mess up the schematic more than crossed-dotted lines.

In your rules, perhaps.