Current leak in Opto-isolator

ay ON with either supply, but you can turn OFF under software control

No, not quite. It only latches ON when the computer asserts GPIO 19. Note there is no direct path to the base of Q3 from +12V, +9.6V, or +5V, so not hing from any power supply can energize Q3, which is the only means of turn ing on O1. GPIO19 is floating until the software asserts it to +3.3V. Oth erwise, R8 makes certain no current flows though D5 and the LED of O1. Onc e the computer shuts down, GPIO 19 once again floats, and the battery is is olated from the rest of the electronics, with the exception of U1, which I must choose carefully so that it won't be killed by having ~10V on its posi tive input and its output with no power to its positive supply rail. A sma ll leakage through U1 - less than 0.1ma, won't be significant.

Reply to
Leslie Rhorer
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dy on, the only control is to turn it off.

Well, not, not if I understand what you are saying. Applying a reasonable positive voltage (in this case 3.3V) to GPIO 19 should turn on O1 and remo ving its will turn it off, no matter what the state of +12V, +9.6V, or +5V. Of course, unless the RPi is powered from an external source, then there is no way to assert GPIO 19, but that's not relevant to this discussion.

a logic lockup flaw.

Uh-uh. At the moment, nothing at all is connected to the board except +9.6 V.

Reply to
Leslie Rhorer

Yes. The problem is continuous.

nternally), so I would verify that oscillations are not fooling your measur ements, and the SSR really is on. Partially, at least some of the time, bu t not enough to light your LED's.

No, it's steady as a rock. I will be re-working the traces later this even ing. We'll see.

If you or anyone else has a simpler solution, I'm all ears, as it were. Th ese are the parameters:

  1. Must be able to deliver 15 Watts at the +5V output
  2. Assume 90% conversion efficiency for the DC-DC converter.
  3. Assume a main power supply between +11.5V and +16V, at least 2V higher than the chosen battery terminal voltage at full charge.
  4. Assume a nominal battery voltage from +7.2V to +13.2V
  5. Assume a shutdown threshold no lower than +6.7V
  6. Must isolate the battery's positive terminal from ground with no more t han 0.1 milliampere of leakage whenever GPIO 19 is floating or tied to grou nd.
  7. Must inform the RPi of mains power failure whenever the voltage drops be low ~9V.
  8. Must trickle charge the battery whenever the mains power is present at a rate of Is this just a battery UPS? "Just"? It is a UPS for a Raspberry Pi, yes, sans the main supply. I also have an ADC which measures the input voltage, Battery voltage, and chargin g current, not shown here.
Reply to
Leslie Rhorer

the MOSFETs and cut RON by half as well as double current rating.

Exactly. In actual use it may or may not be needed. The Raspberry Pi itse lf only uses about 150ma continuous at 5V, depending on which on-board peri pherals are active, but it may have over 2A of attached peripherals. Below 10V input to the converter, it could exceed the relay's specs if the RPi i s heavily loaded.

Yeah, especially not with this converter:

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That goes more than double since in proper operation, the relay will never see an in-rush. The converter will always be fully energized long before G PIO 19 is asserted. Typically almost a minute.

Reply to
Leslie Rhorer

I am very open to any suggestions. I have never used P-MOS. Do you have a part number? Minimum 2A load with the lowest possible voltage drop when a ctive, plus reasonably high isolation when inactive. (Less than 0.1ma leak age) It also should have enough of a trigger current to light an external LED when active. Something on the order of microamp for the trigger curren t won't activate an external indicator LED. The opto-isolator is nice in t hat the same current which lights the internal LED is perfect for an extern al indicator LED. 'Not entirely essential, I suppose, but quite desirable.

tion needs any opto-isolation.

Well, it requires a modest level of isolation. An opto-isolator is an easy and readily available solution.

-on, which avoids high in-rush current, and those chips can detect overloa d to auto-shutdown.

Again, I'm all ears.

Reply to
Leslie Rhorer

I don't consider it "lousy". I much prefer it. It also has nothing to do with the issue at hand.

Reply to
Leslie Rhorer

On the page or in the reader's eye? Wire jumps are much busier and harder to read, especially in a dense design.

Which is more of a good reason to do it than anything else. I don't design for the military, and I am unconcerned with any specifications for documen tation. Such things are just administrative intrusion. Someone trying to either justify their job or satisfy their ego by forcing others to follow t heir arbitrary rules.

Are you able to read the design? If not, you are very free to print it out and put in jumps where the dots exist. Honestly, I am not sure it matters whether or not you can, since so far you have contributed nothing to this discussion but a criticism of my drafting technique, which has nothing to d o with the circuit design. Do you have something to contribute to the desi gn?

Reply to
Leslie Rhorer

r to read, especially in a dense design.

gn for the military, and I am unconcerned with any specifications for docum entation. Such things are just administrative intrusion. Someone trying t o either justify their job or satisfy their ego by forcing others to follow their arbitrary rules.

ut and put in jumps where the dots exist. Honestly, I am not sure it matte rs whether or not you can, since so far you have contributed nothing to thi s discussion but a criticism of my drafting technique, which has nothing to do with the circuit design. Do you have something to contribute to the de sign?

you missed the point, the dots are "fine" it is just the with low resolutio n it can be impossible to tell the difference between a connection and a cr ossing

so in instead of:

|

---o--- |

the preferred ways is:

|

---+ | +---- |

Reply to
Lasse Langwadt Christensen

OK, since apparently some here might have trouble seeing dots represented f or junctions, I went back and increased their size. I am *NOT* going to go into my CADD software and create some symbols that do not already exist ju st to satisfy some literary critics. BTW, what those of you who seem to on ly want to criticize my drafting also seem to be missing is I have quite by long habit laid out the schematic in such a way so there are zero intersec ting lines which are not junctions. ZERO. Far from being bad deign, I con sider it very proper design, indeed. Now lets move on to something that ac tually matters, shall we?

Reply to
Leslie Rhorer

In general I agree, though there have been (many) times where the line density was high enough that doing such would have messed up the schematic completely. Much of that has to do with the way we're forced to draw components but the point is there are reasons to use crosses/dots.

Reply to
krw

I don't think anyone is advocating jumps. But junction dots should be obvious: diameter at-least 4 times the line-width.

Draughting standards help communications to be understood. When it's a matter of life and death, clear communication is essential.

I didn't see obvious dots at the junctions, but I could guess they were all intended as junctions because with them as crossings the layout seemed needlesly convoluted. I had no way to know if you had constructed them as junctions, but junctions seemed most likely. For clarity it's better to avoid four-way junctions. making two tee junctions instead, that way no-one has to guess. A chematic is foremost a communication tool, and anly secondly a piece of artwork.

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Reply to
Jasen Betts

crossings are untidy, I don't like them either, and avoid them except where they help clarity.

When there are no crossings and a stranger encounters an intersection of lines how are they to tell if it's a junction drawn under the "jumps" convention or a crossing drawn under the "dots" convention?

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Reply to
Jasen Betts

Are there other "jumps" or "dots" on the page?

Reply to
krw

not when I looked.

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Reply to
Jasen Betts

No other crossings?

Reply to
krw

through the 12V supply and Q4.

ying the 9.6V battery is the only source of power at this point in testing. I don't see how Q4 could be a culprit in any case. If +12V is on its inp ut, then it will be fully saturated by design, not leaking. If not, then I fail to see how leakage through Q4 would bias O1's LED.

urrent is derived from the 5V DC-DC output???

d the computer and the RPi has asserted GPIO 19 in software. Once done, th e circuit has latched the SSSR through the RPi. If +12V fails, then by the fact the battery is feeding the input of the DC-DC converter, +5V remains intact, and the computer remains active, despite having presumably lost AC power. GPIO 17 informs the computer of the loss of mains power, and at a l ater time it will affect its shutdown procedure. When the computer shuts d own, GPIO 19 is de-asserted, O1 is deactivated, and the battery is isolated from everything.

Okay, the datasheet is not very specific about their test circuit, but most applications use a bleeder resistor across the SSR diode input. Select R f or half minimum diode VF at minimum turn-off current, or about 0.5V at 50uA , making it 10kR across pins 1 & 2. I don't see a leakage source of that m agnitude anywhere in your circuit though. Failing that substitute a new opt o, but test it for basic ON/OFF operation on a plug board first.

Reply to
bloggs.fredbloggs.fred

y through the 12V supply and Q4.

saying the 9.6V battery is the only source of power at this point in testin g. I don't see how Q4 could be a culprit in any case. If +12V is on its i nput, then it will be fully saturated by design, not leaking. If not, then I fail to see how leakage through Q4 would bias O1's LED.

current is derived from the 5V DC-DC output???

ted the computer and the RPi has asserted GPIO 19 in software. Once done, the circuit has latched the SSSR through the RPi. If +12V fails, then by t he fact the battery is feeding the input of the DC-DC converter, +5V remain s intact, and the computer remains active, despite having presumably lost A C power. GPIO 17 informs the computer of the loss of mains power, and at a later time it will affect its shutdown procedure. When the computer shuts down, GPIO 19 is de-asserted, O1 is deactivated, and the battery is isolat ed from everything.

st applications use a bleeder resistor across the SSR diode input. Select R for half minimum diode VF at minimum turn-off current, or about 0.5V at 50 uA , making it 10kR across pins 1 & 2. I don't see a leakage source of that magnitude anywhere in your circuit though. Failing that substitute a new o pto, but test it for basic ON/OFF operation on a plug board first.

you missed the part about the SSR being connected backwards? so it wasn't l eakage it was the bodydiode

Reply to
Lasse Langwadt Christensen

...@gmail.com:

:

nly through the 12V supply and Q4.

n saying the 9.6V battery is the only source of power at this point in test ing. I don't see how Q4 could be a culprit in any case. If +12V is on its input, then it will be fully saturated by design, not leaking. If not, th en I fail to see how leakage through Q4 would bias O1's LED.

ED current is derived from the 5V DC-DC output???

ooted the computer and the RPi has asserted GPIO 19 in software. Once done , the circuit has latched the SSSR through the RPi. If +12V fails, then by the fact the battery is feeding the input of the DC-DC converter, +5V rema ins intact, and the computer remains active, despite having presumably lost AC power. GPIO 17 informs the computer of the loss of mains power, and at a later time it will affect its shutdown procedure. When the computer shu ts down, GPIO 19 is de-asserted, O1 is deactivated, and the battery is isol ated from everything.

most applications use a bleeder resistor across the SSR diode input. Select R for half minimum diode VF at minimum turn-off current, or about 0.5V at

50uA , making it 10kR across pins 1 & 2. I don't see a leakage source of th at magnitude anywhere in your circuit though. Failing that substitute a new opto, but test it for basic ON/OFF operation on a plug board first.

leakage it was the bodydiode

LOL- how is it possible to connect it backwards?

Reply to
bloggs.fredbloggs.fred

.@gmail.com:

te:

ainly through the 12V supply and Q4.

in saying the 9.6V battery is the only source of power at this point in te sting. I don't see how Q4 could be a culprit in any case. If +12V is on i ts input, then it will be fully saturated by design, not leaking. If not, then I fail to see how leakage through Q4 would bias O1's LED.

LED current is derived from the 5V DC-DC output???

booted the computer and the RPi has asserted GPIO 19 in software. Once do ne, the circuit has latched the SSSR through the RPi. If +12V fails, then by the fact the battery is feeding the input of the DC-DC converter, +5V re mains intact, and the computer remains active, despite having presumably lo st AC power. GPIO 17 informs the computer of the loss of mains power, and at a later time it will affect its shutdown procedure. When the computer s huts down, GPIO 19 is de-asserted, O1 is deactivated, and the battery is is olated from everything.

t most applications use a bleeder resistor across the SSR diode input. Sele ct R for half minimum diode VF at minimum turn-off current, or about 0.5V a t 50uA , making it 10kR across pins 1 & 2. I don't see a leakage source of that magnitude anywhere in your circuit though. Failing that substitute a n ew opto, but test it for basic ON/OFF operation on a plug board first.

't leakage it was the bodydiode

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DC only configuration puts the two fets in parallel rather than series to d ouble the current rating

Reply to
Lasse Langwadt Christensen

Maybe add a resistor acress the eb jn of Q4.

You could be getting amplification of Q5 Icbo.

RL

Reply to
legg

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