core memory

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Testing some FTP stuff, threw up some test files...

ftp://jjlarkin.lmi.net/Core_304bits.jpg

ftp://jjlarkin.lmi.net/Core_4K.jpg

ftp://jjlarkin.lmi.net/Core_4Kdetail.jpg

John



Re: core memory


On a sunny day (Sat, 05 Dec 2009 10:51:36 -0800) it happened John Larkin

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16 bits x 19??


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Amazing..



Must have been expensive.


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Re: core memory


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Don't recognise either of those as to manufacturer, but the last machine
that I had with core was an early pdp11/05, which eventually got shipped
back to the us.

Ok, quiz time: how does core memory work ?. (and no cheating via google
etc :-)...

Regards,

Chris

Re: core memory


On a sunny day (Sat, 05 Dec 2009 19:18:45 +0000) it happened ChrisQ

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OK, without cheating, I have never used core memory so...
XY wires, magnetize one core at X,Y.
There is also a read wire, mabe use a lower power to address the one you
want to read, and then the read wire will give a signal depending on
the magnetisation of that specific core..
Or maybe use full power to address, and then write back a 1 if it was a 1,
and a 0 if it was a 0, so opposite magenetisation for 0 and 1.
Not sure.
Something like that.
 
Am watching a weid kung fu movie, so ...

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Re: core memory



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The cores have hysteresis.  You can't flip the direction of magnetisation
unless the current in the wires exceeds a certain threshold.  You put half
the required current down an X wire and half down a Y wire.  Only one core
at the X,Y intersection gets flipped.

When you flip a core, you get a pulse induced in the read wire.  This means
you have to do a destructive read.  If you write a 1 and get a big pulse
back then you know it must have been a 0 before.  If it was already a 1, you
only get a tiny pulse.  Every read must be followed by a write to restore
the previous state.

See my core memory page for 'scope captures of actual read pulses:

http://www.holmea.demon.co.uk/Core/Flipper.htm






Re: core memory



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You usually drove more like 0.6 or so of the required current through
both X and Y, just to make sure...  Also, you had to keep the cores at
a steady operating temperature, which usually meant heating the
enclosure, or pushing warm air through the memory bays at a known
temperature.

Most core planes had one sense line per plane; some had more.  The
sense line is where you (hopefully) sensed the tiny pulse on the read
side that said you'd flipped a bit.

A good friend back in those mainframe days that taught hardware CEs
used to pull sense amp boards, use a solder sucker to remove all the
solder from the sense amp input pins, and then after unplugging his
soldering iron, made the crummiest, coldest connection possible not
really reconnecting the sense amp pin to the trace on the PCB.  Then
he'd spend an inordinate amount of time with emery boards and such
polishing up the connection so it looked all shiny and bright!  Swap
out a good sense amp board with one of those, and you were in for a
load of fun!

Roy, wherever you are, I wish you well!

--

Re: core memory


On a sunny day (Sat, 5 Dec 2009 21:18:35 -0000) it happened "Andrew Holme"

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Cool!


Re: core memory



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Almost square B-H loops.


--
"Electricity is of two kinds, positive and negative. The difference
is, I presume, that one comes a little more expensive, but is more
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Re: core memory



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Pretty good page.  Would you like to discuss drive electronics?
Nothing bigger than a TO-5 needed.  74hc138 decoders are fair game.
46%lat-pack packages ere fair game.

Re: core memory


On Fri, 11 Dec 2009 10:02:20 -0800,

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TI made, for a while, integrated core stack drivers and sense amps.
Ironic that as ICs got good enough to drive and sense cores, ICs got
good enough to kill cores.

Anybody remember 1K drams? I did a color graphic video generator, for
oil/gas/product pipeline controls, using the strange 1K AMS parts. TI
made a driver for them, too. They were differential read/write (5 volt
write, millivolts read) and the memory cell was basically two
capacitors and two connect fets.

John


Re: core memory


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I _almost_ used some DRAMs once, except by the time I got the Z80 board
almost done, they were up to 64K. The Z80 had a "refresh" output, so using
them would have been within the scope of my abilities at the time. ;-)

Ufortunately, the project got interrupted and placed on the back burner,
where it's been ever since. )-;

Cheers!
Rich


Re: core memory


On a sunny day (Fri, 11 Dec 2009 15:02:20 -0800) it happened Rich Grise

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I did a 265 kB RAMDISK with DRAM for the Z80.
 ftp://panteltje.com/pub/z80 /
It was I/O mapped :-)
The refresh was done by having it cycle through 512 address rows when not
addressed.
When addressed 512 bytes were read or written at any time, 'sector size'.
It had write protest logic too, before writing a sector you had to do I/O to the
unlock address.
The procedure was:
 write to unlock address,
 write sector address low
 write sector address high
 write 512 bytes data.
The idea was to read a complete single sided floppy (204800 Bytes = 40 tracks of
10 sectors of 512 bytes)
into this RAMDISK, and then work from the RAMDISK.
It was faster then anything at that time when doing that.
Ran a C compiler on it, almost faster then the PC these days.
4 MHz clock.

Re: core memory


On Fri, 11 Dec 2009 12:41:42 -0800, John Larkin

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Are you referring to the 1103 ?

Quite awful chip.

The next generation 4 K dynamic or 1 K static were much easier to use.

 

Re: core memory



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No, I used an AMS part, 6002 I think. It had essentially two
capacitors and two fets per cell, possibly structured as a
4-transistor dynamic latch with two access transistors. Either way,
one wrote to it by applying a differential 5-volt level to a pair of
pins, charging the addressed cell. Read connected to the same cell,
and you got back a small differential signal. Actually, the chip
didn't care whether you were reading or writing... it just connected
you to the pair of caps. Read was destructive, like core, so after a
read you had to recharge the caps then disconnect. It was noisy, like
core.

I've heard similarly bad stories about the 1103.

Interesting: one of the founders of AMS was J. Larkin:

http://www.computerhistory.org/semiconductor/companies.html


John


Re: core memory



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I still have a PDP 11/05 core unit hanging on my wall along witg a
disk platter and a few other things from that machine.

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Re: core memory


On a sunny day (Sat, 05 Dec 2009 20:10:52 -0500) it happened PeterD


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I have a DVD+R hanging on the wall, shiny side front, looks
nice, stores more data.
Do not remember what is on it.

Re: core memory



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Even though i am nearly a week behind, i gotta step up to the plate.

The most common form of core memory is called 3D.  It is made up of
bit planes (the third dimension).  The cores have a very square B-H
curve.  In the bit planes there X and Y direction drive wires.
Coincident current through the two wires produces enough field to make
the addressed core switch direction of magnetization.  The current
pulse times are usually no longer than enough to ensure reliable
operation.  No other cores in the plane receive enough drive current
induced flux to change state.  Thus we need to add a sense wire to
detect the core flux state changes.  The sense wires are typically
done diagonally to take advantage of the slightly larger aperture in
that direction. 20%

Since the mechanism to readout the value of the core forces it to
either the "0" or "1" state (a design property) any information to
remain in the address must be rewritten.  Thus another wire called
inhibit which is wired in parallel with either the X or the Y drive
lines and is driven with an opposing current flow which prevents
changing the state of the core on the writeback half cycle. 20%

This allows three typical cycles read-writeback, read(erase)-write,
and read-alter-write.  These are the external interface definitions
and read-alter-write may not be implemented.

I hope that have not omitted too much.

Re: core memory


On Fri, 11 Dec 2009 09:52:35 -0800,

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Perhaps this is just a naming convention, but isn't read-alter-write
the same as read-modify-write naming convention used by some other
manufacturers ?

After all, in current DRAMs, when the RAS signal is asserted, the data
is read from all columns to a common area to be written back to the
memory cells in the same row. When the CAS drops, only the interesting
data is selected in the output multiplexer.

 

Re: core memory



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It is really just a difference in names.
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In the oldest versions.  Then they changed things and you could get four20%
successive address more quickly.  This was called EDO DRAM about 20 years=
20%
ago.  Since then things have gone further in that direction.  Gotta keep20%
the caches fed so that they can feed the core.

Re: core memory


On Sat, 05 Dec 2009 19:03:54 GMT, Jan Panteltje

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I remember when IBM announced that they had reduced the price of
mainframe core to below $50,000 per megabyte. I was very young at the
time, of course.

John


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