Connecting FLASH memory device on printed circuit board

Hi everyone,

I am new to the board design and stuff so please excuse me for asking questions that may be selfevident... ;-) What I want to do is to connect an Intel StrataFlash (or compatible) linear flash memory device (8MB) to an Intel PXA26x processor. Now I wonder if I should pay attention to the impedance (some time ago I heard a weird fairy tale saying that everything on board should be designed to 50 Ohms...?!) on the lines that connect the devices or just design some connections no matter how and let a matter rest. What I really want to know is not only "yes" or "no" or "doesn't matter", but a sophisticated statement that explains to me why it is that way or the other and when the impedance does matter?

Hope anyone can help me out of this misery. Thank you in advance for any helpful advice.

Norman

Reply to
Norman Bollmann
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Is this chip still available? I've heard the PXA was sold to another company and Intel isn't producing it anymore.

I don't know the details, but I know a company, who needed about one year (2 man years) to design a board with a PXA, Flash and SDRAM. Many tries were needed to do the routing right, adding buffers, measuring with expensive logic analyzers and oscilloscopes etc. I hope you are working at a big company, who has the knowledge and power to design such a board and to do bug searching at 100 MHz, or faster, buses.

--
Frank Buss, fb@frank-buss.de
http://www.frank-buss.de, http://www.it4-systems.de
Reply to
Frank Buss

The fact that there is almost no response tells me that it REALLY IS more complicated than I thought and no one is in the know ... :-(

Reply to
Norman Bollmann

What sort of speeds are you dealing with? Under 100MHz with rise times that aren't too fast shouldn't require anything special. We're running

64MB DDR2 at 200MHz clock rates with no terminations. It's amazing how beautiful the signals look.

The trick to our madness is using only one memory chip per bus connection and keeping the connections short. On our board, the longest trace between the FPGA and the memory is 0.800". Our flash memory is less stringent, so some of the traces are 1.5". Any of the edge sensitive lines are kept as short as practical. You may consider putting terminations on the clock lines if the trace lengths get too long.

This technique will fall apart if you gang multiple memory devices. The key here is no stub connections in the middle of the trace and short runs.

All of our traces were sandwiched between power and ground planes mainly to reduce EMI. Something that is really helpful is being able to control the rise/fall times of your signals. On an FPGA, no problem. Unfortunately, I don't think your processor has variable drive control.

As to trace impedance, around 50 to 100 ohms is want you want to aim for. You're kind of forced into the 50 to 100 ohm region by virtue of the practical aspects of the PCB layout. We're getting about 50 ohms on or our boards using 5 mil trace width buried between two planes with 8 mil separation between the layers for single ended traces and around 100 ohms for the differential clock signals. On some of our boards, we design 100 ohm differential traces for signals running on LVDS. With LVDS, you're stuck designing to 100 ohms if you want to stay within bounds of the spec.

-- Mark

Reply to
qrk

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