CMOS Divide by 5.9 Cicuit

Oh, that's very different from what you asked for at the start.

This is a waste of time. Tell us what you're really trying to do or go away.

Jeroen Belleman

This could be solved by using numerically controlled oscillators

in which there is an NCO for each frequency.

For square output, but approximately 50 % duty cycle digital output, you could use the highest bit of the phase accumulator as the digital output.

For sine wave output, use the highest bits of the phase accumulator to address a sine table and use the acquired value to run a DAC/PWM output and some passive RC filtering for clean sine wave.

Of course, this can be done with CD4000 series chips, but the cost will increase rapidly with the number of frequencies required.

If you are not familiar with microconrollers, this might be a good opportunity to learn how to do some simple things using a microcontroler.

You would need a very primitive microcontroller clocked at about 1-3 MHz from any free running oscillator. The 16 to 32 bit phase accumulators are updated each time the 32768 Hz precise oscillator changes state. For digital output, you need just one digital output pin, for analog output, he chips should have pins with DAC or PWM outputs.

The additional cost for any additional frequency output is just a software accumulator (2 to 4 bytes) and one output pin (or even less, if an external analog/digital demultiplexer is used.

4Hz is much easier than 5.9.

You need to use a 4046 or other PLL chip, and synthesize multiples of some reference frequency. Then either use that, or divide it down to your desired frequency.

To get 4, 8, 12, etc., you probably want to synthesize multiples of your crystal clock (so your PLL will settle quickly), then divide the result down.

Google "frequency synthesis". The short story is that you take the output of the PLL chip and divide it by n, then phase lock the (PLL/n) signal to the reference. As long as the PLL stays locked, its output will be n * reference. There's all sorts of jiggery-pokery you'll need to do to get the PLL to work right, compounded by the fact that the easily available

4046 derivatives have oscillators that tend to misbehave at low frequencies (ask here about the specifics -- I can't remember them).

You're probably looking at a 74HCU04 for the reference oscillator, a

74HC4046 PLL, a 74HC161 divider chip, some NAND gates (I vaguely recall that you need them if you want to turn the '161 into a divide-by-n chip), and your 4060.

Or, you can do it all with an 8-pin PIC or other 8-pin microprocessor: it's your choice.

--

Tim Wescott 
Wescott Design Services 
http://www.wescottdesign.com

Not really. An arb wave was what was going to be created from the derived signals. At this stage I was looking for a compromise.

Well, I did learn something, and perhaps others did too. There were a number of answers I found very helpful.

Having seen the alternatives, I have decided I can get close enough using a CD4060 and a CD4017.

OK I am going now. Thanks again.

Ken Knowles

the simpler solution is a microcontroller with "four or five" 16-bit counters that can drive output pins,

I think atmel do some 8 some bit AVR microcontrollers with 4 to 6 counters

however it's a bit more delicate, it won't run off 3 to 15V like tha

4060 does, And while it doesn't use a lot of power, it still uses more than the 4060. even with the core halted and only the counters running

another option is a microcontroller running off a faster clock and doing the frewquency division in software, it'll use more power, be harder to program, but may allow cheaper parts.

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umop apisdn 


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Or just get one or two frequencies from a microcontroller, in which case there are many choices. Computers are cheap in 2014, no need to make them do a lot of work.

For example, a PIC18F24J10 can generate two frequencies from a 10MHz clock for ~$1.50 each in 25's. The compare registers are only 16 bits so you'd have to count hits to get 100ns resolution at 16Hz, but that's just a few lines of code.

Best regards, Spehro Pefhany

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If you do not want to use a microcontroller and the NCO principle, you are forced to divide down to the frequency spacing frequency (4 Hz or

32 Hz) and then use individual PLLs for each frequency.

In practical circuits, use something like 256x or 1000x reference frequency and then use the same amount of division after _each_ PLL.