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Re: CMOS Divide by 5.9 Cicuit

On 20 Aug 2014 08:51:01 GMT, "Peter Heitzer"

I am sorry my orignal explanation was unclear to some readers.

It is easy to generate 32Hz with a 32,768 clock crystal and a CD4060.

I then would like to produce from this four or five frequencies that

all differ by the same number of Hz.

To take a simple example, if that was 4Hz I would get 28, 24, 20,

16Hz, and so on.

Since coding is not one of my skills, can this be done with logic

IC's? Maybe something involving sums and differences.

I could also use a separate generator for each frequency, but was

hoping for a more efficient method, if there is one.

Ken Knowles

I am sorry my orignal explanation was unclear to some readers.

It is easy to generate 32Hz with a 32,768 clock crystal and a CD4060.

I then would like to produce from this four or five frequencies that

all differ by the same number of Hz.

To take a simple example, if that was 4Hz I would get 28, 24, 20,

16Hz, and so on.

Since coding is not one of my skills, can this be done with logic

IC's? Maybe something involving sums and differences.

I could also use a separate generator for each frequency, but was

hoping for a more efficient method, if there is one.

Ken Knowles

Re: CMOS Divide by 5.9 Cicuit

On 20/08/14 23:14, Ken Knowles wrote:

So, in clear language, you'd like to create 32Hz, 26.1Hz, 20.2Hz,

14.3Hz, etc, down to ???, from one 32768Hz source, all with 50%

duty cycle. That's probably not trivial in old-fashioned logic,

but a multiple DDS algorithm in a tiny microcontroller could come

pretty close with relative ease.

Do you mind telling us why you want to do so? Often the

problem is easier to solve that someone's weird idea of a

solution.

Jeroen Belleman

So, in clear language, you'd like to create 32Hz, 26.1Hz, 20.2Hz,

14.3Hz, etc, down to ???, from one 32768Hz source, all with 50%

duty cycle. That's probably not trivial in old-fashioned logic,

but a multiple DDS algorithm in a tiny microcontroller could come

pretty close with relative ease.

Do you mind telling us why you want to do so? Often the

***real***problem is easier to solve that someone's weird idea of a

solution.

Jeroen Belleman

Re: CMOS Divide by 5.9 Cicuit

Since I don't have coding skills, it seems the opnly viable solutuion

is to build a separate generator for each frequency. "

Are you measuring output from subwoofers ?

If you are trying to get better than the pink noise method, you have to filter the input, to where it does not pick up harmnics of the frequency put into the woofer.

If the application is something else, sorry to waste your time.

but I did not notice the exact purpose of this device. Maybe you got your reasons.

Re: CMOS Divide by 5.9 Cicuit

On Wednesday, August 20, 2014 7:04:14 PM UTC-7, Ken Knowles wrote:

The problem is, 32 Hz has a period of 0.312500 seconds, which is

1024 'ticks' of a 32768 Hz clock. And 26.1 Hz has a period of

.03831417625 seconds, which is 1255.478927.. ticks of that clock. There's

no digital way to directly generate frequencies without approximations,

unless the frequencies of interest line up 'just right' with your digital

clock.

The problem is, 32 Hz has a period of 0.312500 seconds, which is

1024 'ticks' of a 32768 Hz clock. And 26.1 Hz has a period of

.03831417625 seconds, which is 1255.478927.. ticks of that clock. There's

no digital way to directly generate frequencies without approximations,

unless the frequencies of interest line up 'just right' with your digital

clock.

Re: CMOS Divide by 5.9 Cicuit

wrote:

This could be solved by using numerically controlled oscillators

http://en.wikipedia.org/wiki/Numerically

which there is an NCO for each frequency.

For square output, but approximately 50 % duty cycle digital output,

you could use the highest bit of the phase accumulator as the digital

output.

For sine wave output, use the highest bits of the phase accumulator to

address a sine table and use the acquired value to run a DAC/PWM

output and some passive RC filtering for clean sine wave.

Of course, this can be done with CD4000 series chips, but the cost

will increase rapidly with the number of frequencies required.

If you are not familiar with microconrollers, this might be a good

opportunity to learn how to do some simple things using a

microcontroler.

You would need a very primitive microcontroller clocked at about 1-3

MHz from any free running oscillator. The 16 to 32 bit phase

accumulators are updated each time the 32768 Hz precise oscillator

changes state. For digital output, you need just one digital output

pin, for analog output, he chips should have pins with DAC or PWM

outputs.

The additional cost for any additional frequency output is just a

software accumulator (2 to 4 bytes) and one output pin (or even less,

if an external analog/digital demultiplexer is used.

This could be solved by using numerically controlled oscillators

http://en.wikipedia.org/wiki/Numerically

___controlled___oscillator inwhich there is an NCO for each frequency.

For square output, but approximately 50 % duty cycle digital output,

you could use the highest bit of the phase accumulator as the digital

output.

For sine wave output, use the highest bits of the phase accumulator to

address a sine table and use the acquired value to run a DAC/PWM

output and some passive RC filtering for clean sine wave.

Of course, this can be done with CD4000 series chips, but the cost

will increase rapidly with the number of frequencies required.

If you are not familiar with microconrollers, this might be a good

opportunity to learn how to do some simple things using a

microcontroler.

You would need a very primitive microcontroller clocked at about 1-3

MHz from any free running oscillator. The 16 to 32 bit phase

accumulators are updated each time the 32768 Hz precise oscillator

changes state. For digital output, you need just one digital output

pin, for analog output, he chips should have pins with DAC or PWM

outputs.

The additional cost for any additional frequency output is just a

software accumulator (2 to 4 bytes) and one output pin (or even less,

if an external analog/digital demultiplexer is used.

Re: CMOS Divide by 5.9 Cicuit

On Thu, 21 Aug 2014 07:14:07 +1000, Ken Knowles wrote:

4Hz is much easier than 5.9.

You need to use a 4046 or other PLL chip, and synthesize multiples of some

reference frequency. Then either use that, or divide it down to your

desired frequency.

To get 4, 8, 12, etc., you probably want to synthesize multiples of your

crystal clock (so your PLL will settle quickly), then divide the result

down.

Google "frequency synthesis". The short story is that you take the output

of the PLL chip and divide it by n, then phase lock the (PLL/n) signal to

the reference. As long as the PLL stays locked, its output will be n *

reference. There's all sorts of jiggery-pokery you'll need to do to get

the PLL to work right, compounded by the fact that the easily available

4046 derivatives have oscillators that tend to misbehave at low

frequencies (ask here about the specifics -- I can't remember them).

You're probably looking at a 74HCU04 for the reference oscillator, a

74HC4046 PLL, a 74HC161 divider chip, some NAND gates (I vaguely recall

that you need them if you want to turn the '161 into a divide-by-n chip),

and your 4060.

Or, you can do it all with an 8-pin PIC or other 8-pin microprocessor:

it's your choice.

4Hz is much easier than 5.9.

You need to use a 4046 or other PLL chip, and synthesize multiples of some

reference frequency. Then either use that, or divide it down to your

desired frequency.

To get 4, 8, 12, etc., you probably want to synthesize multiples of your

crystal clock (so your PLL will settle quickly), then divide the result

down.

Google "frequency synthesis". The short story is that you take the output

of the PLL chip and divide it by n, then phase lock the (PLL/n) signal to

the reference. As long as the PLL stays locked, its output will be n *

reference. There's all sorts of jiggery-pokery you'll need to do to get

the PLL to work right, compounded by the fact that the easily available

4046 derivatives have oscillators that tend to misbehave at low

frequencies (ask here about the specifics -- I can't remember them).

You're probably looking at a 74HCU04 for the reference oscillator, a

74HC4046 PLL, a 74HC161 divider chip, some NAND gates (I vaguely recall

that you need them if you want to turn the '161 into a divide-by-n chip),

and your 4060.

Or, you can do it all with an 8-pin PIC or other 8-pin microprocessor:

it's your choice.

--

Tim Wescott

Wescott Design Services

Tim Wescott

Wescott Design Services

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Re: CMOS Divide by 5.9 Cicuit

the simpler solution is a microcontroller with "four or five" 16-bit

counters that can drive output pins,

I think atmel do some 8 some bit AVR microcontrollers with 4 to 6

counters

however it's a bit more delicate, it won't run off 3 to 15V like tha

4060 does, And while it doesn't use a lot of power, it still uses more

than the 4060. even with the core halted and only the counters running

another option is a microcontroller running off a faster clock and doing

the frewquency division in software, it'll use more power, be harder to

program, but may allow cheaper parts.

--

umop apisdn

umop apisdn

Re: CMOS Divide by 5.9 Cicuit

Or just get one or two frequencies from a microcontroller, in which

case there are many choices. Computers are cheap in 2014, no need to

make them do a lot of work.

For example, a PIC18F24J10 can generate two frequencies from a 10MHz

clock for ~$1.50 each in 25's. The compare registers are only 16 bits

so you'd have to count hits to get 100ns resolution at 16Hz, but

that's just a few lines of code.

Best regards,

Spehro Pefhany

--

"it's the network..." "The Journey is the reward"

snipped-for-privacy@interlog.com Info for manufacturers: http://www.trexon.com

"it's the network..." "The Journey is the reward"

snipped-for-privacy@interlog.com Info for manufacturers: http://www.trexon.com

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Re: CMOS Divide by 5.9 Cicuit

wrote:

If you do not want to use a microcontroller and the NCO principle, you

are forced to divide down to the frequency spacing frequency (4 Hz or

32 Hz) and then use individual PLLs for each frequency.

In practical circuits, use something like 256x or 1000x reference

frequency and then use the same amount of division after

If you do not want to use a microcontroller and the NCO principle, you

are forced to divide down to the frequency spacing frequency (4 Hz or

32 Hz) and then use individual PLLs for each frequency.

In practical circuits, use something like 256x or 1000x reference

frequency and then use the same amount of division after

___each___PLL.Re: CMOS Divide by 5.9 Cicuit

On 20 Aug 2014 08:51:01 GMT, "Peter Heitzer"

I think I may have figured out a way to get something close to the

result I am looking for.

The CD4060 with a 32,768Hz crystal will output a 32, and 8Hz

squarewave.

If I filter these into sine waves, what is the procedure for having

them along with their sum and difference frequencies all together in

one signal?

IOW to end up with a repetitive arbitrary waveform comprised of 40,

32, 27 and 8Hz.

Ken Knowles

I think I may have figured out a way to get something close to the

result I am looking for.

The CD4060 with a 32,768Hz crystal will output a 32, and 8Hz

squarewave.

If I filter these into sine waves, what is the procedure for having

them along with their sum and difference frequencies all together in

one signal?

IOW to end up with a repetitive arbitrary waveform comprised of 40,

32, 27 and 8Hz.

Ken Knowles

Re: CMOS Divide by 5.9 Cicuit

take 32 and 'multiply' it 8 in something like a MC1496

if done well, that will produce 40, 32, 27, and 8

a MUCH simpler way is to drive your stupid soundcard with a .wav

repetitively. use the standard 48kS/s to be an EXACT multiple, use octave

to make the .wav file and you can get equal amplitude ANY phase you want,

complete control and not even have to breadboard anything. All these tools

are FREE to work with, too.

Re: CMOS Divide by 5.9 Cicuit

Completely the wrong approach.

Assuming it is

***ESSENTIAL***to lock the frequency to the 32768 Hz crystal,

I'd start by squaring it up and doubling the frequency with a RC delay

and an XOR. Then use a programmable divider chip (or rather chips as

you'll probaby need to cascade them) to get pulses at a rate as close as

possible to N*11.8 Hz.

Finaly a flipflop divides by two to get a good square wave.

If you dont need to start with 32768 Hz, its much more accurate if you

use a significantly higher crystal frequency - at the expense of needing

a longer divider chain and more bits for the division ratio to program

it.

You need some way of storing the division ratio which could be programmed

with a hard wired diode matrix + a 10 way rotary switch (for n=1 to 10)

to ground one column at a time of the matrix, with the rows giving the

binary division ratio.

Ditch the 4060, its no help at all. The oscillator can be built from the

spare gates on the XOR.

However all this grief and considerable expense could be avoided if you

can call in any favours to get someone to write a suitable program for a

small PIC and program one for you.

--

Ian Malcolm. London, ENGLAND. (NEWSGROUP REPLY PREFERRED)

ianm[at]the[dash]malcolms[dot]freeserve[dot]co[dot]uk

Ian Malcolm. London, ENGLAND. (NEWSGROUP REPLY PREFERRED)

ianm[at]the[dash]malcolms[dot]freeserve[dot]co[dot]uk

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Re: CMOS Divide by 5.9 Cicuit

I hope you meant 24, not 27.

This is NOT a digital composition. A roughly square waveform may be

possible that contains arbitrarily few lower harmonics (e.g., a magic

sinewave approximation), but I doubt it is near trivial to compose from

the source frequencies alone.

You've also suddenly changed your requirement, as I don't see how 40, 32,

24 (or 27) or 8 have anything whatsoever to do with 5.9 as a subtractive

or divisive factor.

Perhaps if you could tell us a little about the underlying enigmatic

purpose, we could suggest something both better suited and easier to

construct.

Tim

--

Seven Transistor Labs

Electrical Engineering Consultation

Seven Transistor Labs

Electrical Engineering Consultation

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Re: CMOS Divide by 5.9 Cicuit

Also, this is required reading:

https://groups.google.com/d/msg/sci.electronics.design/d2OahQyjH84/Pob_iHtHAKMJ

Please be considerate in your questions and replies.

Tim

https://groups.google.com/d/msg/sci.electronics.design/d2OahQyjH84/Pob_iHtHAKMJ

Please be considerate in your questions and replies.

Tim

--

Seven Transistor Labs

Electrical Engineering Consultation

Seven Transistor Labs

Electrical Engineering Consultation

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