Classic bootstrap buffer

That's nice. My only concern is that the current through Q1 is not well defined, so the drain voltage won't be predictable.

Why not just a voltage divider into the base of the cascode?

A bypassed bandgap zener thing riding on OUT could set the Q3 base voltage. That eliminates Q1, R7, C2.

--

John Larkin         Highland Technology, Inc 

lunatic fringe electronics

And it's better without C1.

--

John Larkin         Highland Technology, Inc 

lunatic fringe electronics

The FET drain current has negative tempco, while the BJT has a positive tempco; I'm guessing there's some combination of resistor values that will minimize the drift of IQ1 over temperature. Assuming the intrinsic spread of Vgs->Id curves between devices isn't too extreme...

Making C1 similar in value to the boostrap capacitor and connecting it to the output node instead of ground improves the voltage gain and makes it draw an approximately constant supply current when not loaded down.

nm, just take it out entirely. It is just better without it!

This is a pretty kickass bootstrap buffer.

There's a small dip in the frequency response where it's hitting the self-resonant frequency of the U1 bandgap regulator, I think, around 400kHz

Version 4 SHEET 1 956 1052 WIRE -128 -784 -128 -832 WIRE 320 -784 -128 -784 WIRE 736 -784 320 -784 WIRE -128 -640 -128 -784 WIRE 736 -448 736 -784 WIRE -384 -432 -384 -464 WIRE -128 -400 -128 -560 WIRE 672 -400 -128 -400 WIRE -384 -320 -384 -352 WIRE -384 -320 -480 -320 WIRE 320 -320 320 -784 WIRE -384 -304 -384 -320 WIRE -480 -288 -480 -320 WIRE -384 -176 -384 -224 WIRE -128 -144 -128 -400 WIRE 64 -96 -64 -96 WIRE 320 -96 320 -256 WIRE 320 -96 64 -96 WIRE 464 -96 320 -96 WIRE 736 -96 736 -352 WIRE 736 -96 528 -96 WIRE 64 48 64 -96 WIRE 320 48 320 -96 WIRE -128 80 -128 -48 WIRE -368 144 -608 144 WIRE -176 144 -368 144 WIRE -608 176 -608 144 WIRE -368 176 -368 144 WIRE -128 240 -128 176 WIRE 320 240 320 128 WIRE 320 240 -128 240 WIRE 736 240 736 -96 WIRE 736 240 320 240 WIRE 848 240 736 240 WIRE -608 304 -608 256 WIRE -368 304 -368 256 WIRE -128 336 -128 240 WIRE 736 336 736 240 WIRE 736 480 736 416 WIRE -128 512 -128 416 WIRE 64 576 64 128 WIRE 64 576 -80 576 WIRE -128 688 -128 608 WIRE 64 688 64 576 WIRE -128 864 -128 768 WIRE 64 864 64 768 FLAG -128 -832 Vdd FLAG -384 -464 Vdd FLAG -384 -176 Vss FLAG -480 -288 0 FLAG -128 864 Vss FLAG -608 304 0 FLAG 848 240 Out IOPIN 848 240 Out FLAG 736 480 0 FLAG -368 304 0 FLAG 64 864 Vss SYMBOL njf -176 80 R0 SYMATTR InstName J1 SYMATTR Value 2N5484 SYMBOL njf -80 512 M0 SYMATTR InstName J2 SYMATTR Value 2N5485 SYMBOL res -144 672 R0 SYMATTR InstName R1 SYMATTR Value 470 SYMBOL res -384 160 R0 SYMATTR InstName R2 SYMATTR Value 1Meg SYMBOL pnp 672 -352 M180 SYMATTR InstName Q2 SYMATTR Value 2N3906 SYMBOL res -144 -656 R0 SYMATTR InstName R3 SYMATTR Value 1k SYMBOL voltage -384 -448 R0 WINDOW 123 0 0 Left 2 WINDOW 39 0 0 Left 2 SYMATTR InstName V1 SYMATTR Value 12 SYMBOL voltage -384 -320 R0 WINDOW 123 0 0 Left 2 WINDOW 39 0 0 Left 2 SYMATTR InstName V2 SYMATTR Value 12 SYMBOL res -144 320 R0 SYMATTR InstName R4 SYMATTR Value 1k SYMBOL voltage -608 160 R0 WINDOW 123 24 124 Left 2 WINDOW 39 0 0 Left 2 SYMATTR Value2 AC 1 SYMATTR InstName V3 SYMATTR Value SINE(0 0 100k) SYMBOL npn -64 -144 M0 SYMATTR InstName Q3 SYMATTR Value 2N3904 SYMBOL res 720 320 R0 SYMATTR InstName R8 SYMATTR Value 1k SYMBOL References\\LT1389-5 320 -288 R0 SYMATTR InstName U1 SYMBOL cap 528 -112 R90 WINDOW 0 0 32 VBottom 2 WINDOW 3 32 32 VTop 2 SYMATTR InstName C1 SYMATTR Value 1n SYMBOL res 304 32 R0 SYMATTR InstName R6 SYMATTR Value 10k SYMBOL res 48 32 R0 SYMATTR InstName R7 SYMATTR Value 47k SYMBOL res 48 672 R0 SYMATTR InstName R9 SYMATTR Value 4.7k TEXT -744 376 Left 2 !;ac oct 20 100 100Meg TEXT -856 -8 Left 2 !.tran 0.1

It "bootstraps" it's own quiescent current, too

There's only millivolts across R6. It works in Spice but won't work in real life.

C1 isn't needed, and can't affect DC behavior. R4 isn't useful either.

--

John Larkin         Highland Technology, Inc 

lunatic fringe electronics

Rev 2 is up...

That doesn't work well. The bandgap is shorting out the bootstrap drive.

Bootstrapping is cool, so do it twice:

--

John Larkin         Highland Technology, Inc 

lunatic fringe electronics

Right, the current-limiting resistor is in the wrong position.

Third time's a charm!

You'd get the best capacitance-bootstrapping effect if the top resistor were somehow a big inductor with huge AC resistance but only "appropriately sized" DC resistance.

Where do I get one of those

The upper and lower bandgap bias resistors do load the fet output a little. If the jfet Gm is 25 mS, the fet source looks like 40 ohms, and a couple of 10K resistors would drop the gain about 1%. The resistors can be replaced by current sources if that matters. Your PNP booster transistor can be one of those current sources.

--

John Larkin         Highland Technology, Inc 

lunatic fringe electronics

Make it, of course:

(Speaking of sim models, BTW, this amp boasted 300MHz bandwidth in SPICE, but only a mere 100MHz IRL.)

Tim

--
Seven Transistor Labs, LLC 
Electrical Engineering Consultation and Contract Design 
Website: http://seventransistorlabs.com

On Saturday, May 20, 2017 at 12:44:19 PM UTC-7, John Larkin wrote: ..

...

Couldn't you change the PNP to an NPN based constant current source and avoid the FET having to drive the resistor feeding the bottom zener?

kevin

Sure, that works too. The resistor loading will be small, no problem unless you want Hobbsonian gain levels.

Bootstrap current sources are cool, though. Resistors have pretty low capacitances.

--

John Larkin         Highland Technology, Inc 

lunatic fringe electronics

Analogously, you can make a shunt current source, too:

Rt is the current sink. It's a shitty one, so an error amp (or its own Vbe) controls Qsh to suck up the extra current. These are shown with voltage feedback via Rc, but a current feedback topology would work better. You could also use a current transformer to bootstrap it at AC.

Not that you'd actually want to do that in practice. :)

Tim

--
Seven Transistor Labs, LLC 
Electrical Engineering Consultation and Contract Design 
Website: http://seventransistorlabs.com

As I found out an NPN current source doesn't have the nice property that both the FET Vds and drain current remain approximately constant at all points of the swing.

On my "Revision 3" I changed up the topology a little bit: used the PNP current source JL has instead of the NPN I had, but kept the second upper PNP gain stage also using the lower PNP current source as its load with 100% feedback applied, so you don't have to run large amounts of quiescent current through the FET to get a good amount of drive current.

My Rev 3 AC analysis looks pretty great: nearly completely flat 0.0 dB of gain and no more than 10 degrees of phase shift into a 1k load out to

50 Mhz with those jellybeans

Wow, that must be some microphone!

In the previous circuit, if the drain-source voltage remains approximately constant due to bootstrapping the drain, you'd want to bias the FET current in the triode region where it's most linear, yeah?