capacitive loading an opamp

A few opamps are specifically spec's to drive any capacitive load, like LM8261 for instance. And sometimes you'll see an opamp that is loaded with a big cap to ground, in an appnote for example.

If an opamp has some internal compensation node, midway through, that's the dominant pole, adding a cap on the output makes a second pole in the loop, potentially unstable. A huge cap might be stable, but its corner frequency (with the opamp open-loop output impedance) would have to be absurdly low. ESR matters, too.

Lots of rail-rail opamps have common-emitter output stages, with a PNP emitter on V+ and an NPN emitter on V-, with the collectors being the output. Compensation is often C-B caps on both transistors (or equivalent), so the output is basically a current source with a bunch of Miller capacitance. In that case, and external load cap basically parallels the Miller capacitance, reducing GBW but not adding phase shift.

So there ought to be lots of cheap R-R opamps around that are happy with capacitive loads. Right?

John

Reply to
John Larkin
Loading thread data ...

My experience, right down there at the device level, is that capacitive loading of rail-to-rail OpAmps can still be a "thriller", particularly with large open-loop gains. The problem is that the "Miller", while helpful, is NOT the only internal pole of concern. ...Jim Thompson

--
| James E.Thompson, CTO                            |    mens     |
| Analog Innovations, Inc.                         |     et      |
 Click to see the full signature
Reply to
Jim Thompson

App notes are sometimes written by rookies. I learned that early on when I met a guy who got his degree at the same time as I did. We met by chance at some airport or train station, right after picking up our degrees. This guy had zero hobby experience, didn't even own a solder iron or anything in parts.

"So what are you doing?" ... "Working at XYZ" ... "Oh, cool, but too big a company for me. What kind of projects?" ... "I am writing application notes".

My jaw dropped.

It's not enough and the datasheets still have the same kind of warnings, and limit values. See section 4.3:

formatting link

--
Regards, Joerg

http://www.analogconsultants.com/
Reply to
Joerg

Actually, I like the common emitter types. If you look close at the circuit they usually have some opposite sex transistor hanging off the output collectors going back in the bias circuit. This makes it easy to quench the output if it does not agree with said bias set point. It can capture unexpected voltages being present at the output and clamp it to its desire set point.

Plus they work much better for rail operations.

The ones that use both NPN for both rails I find seem to have better specs for the output, not sure why that is? I do know PNP's are usually the first to go in anything power from my experience.

Jamie

Reply to
Jamie

I figured that out while I was still in high school- that app notes were generally not written by anyone resembling a practicing engineer. Mostly by being bitten by their example circuits.

Best regards, Spehro Pefhany

--
"it's the network..."                          "The Journey is the reward"
speff@interlog.com             Info for manufacturers: http://www.trexon.com
 Click to see the full signature
Reply to
Spehro Pefhany

With a few notable exceptions like Jim Williams. I really miss his crumby scope photos and clear writing style that not only sold parts but helped us to understand WHY things worked. There are many trade-offs in a design and understanding the basics puts a value on those choices.

Oppie

Reply to
Oppie

"Jamie" wrote in message news:8nuLq.16$ snipped-for-privacy@newsfe01.iad...

Minus the extra Vbe drop of course.

Gist of it is, if you start with a doped substrate, then it's real easy to build all the same type transistors on it, and less easy to build the other type. Doing so requires either 1. alternate construction methods, or 2. an extra layer (masking, doping, diffusion, epitaxy, whatever). 1 is almost always preferred over 2, because 2 is very expensive (if you only need 4 masks or whatever, adding another basically increases your development cost by 25%).

For NPNs, they start with a weakly doped P substrate. It's easy to over-dope this to turn it into a reasonably pure N region, without compromising leakage, breakdown voltage or resistivity very much. These become the collector junctions. Further doping pushes a spot in the collector back to P, making the base, and an even smaller, denser blob of doping pushes a spot in the base back to N, forming the emitter and completing the N-P-N transistor.

Note that the substrate is P, so if you generate a substrate current, you forward bias the P-N-P-N parasitic thyristor. This is true of most fabrication processes (bipolar and CMOS), and careful design is required to degenerate this structure to provide reasonable freedom from latchup. Things like wells (extra deep diffusions), guard rings (extra junctions around transistors and wells), trench oxide (cuts into the semiconductor, plugged with glass) and other stuff come in handy here.

If you want to make a PNP in the same method, you either have to settle for placing it on the substrate (substrate collectors probably aren't too handy, and pushing current into the substrate is similar to moving your toilet into your living room and flushing it), or making an additional well, inside the well you originally made, making a 5-layer transistor (P substrate, N well, PNP; just as the substrate gets connected to GND, the N-well gets connected to the highest voltage around, usually VCC). This is the expensive way, because you need another mask to dope the P emitter, and the performance is lower because you have excessive doping (the PNP collector is identical to the NPN's emitter, which might break down at 7V or so; needless to say, the PNP emitter will have even lower breakdown, just a few volts, similar to an RF transistor's E-B junction).

So that said, what's usually done is, you basically take your regular N-P-N transistor, but make two bases, right next to each other. Now, the N well (that used to be the NPN collector) serves as the base. Now, the layers aren't nested like Russain dolls -- current flows sideways from emitter to collector (hence, "lateral PNP"), so the hFE is crap, but on the upside, the "collector" and "emitter" are both the same P-stuff the NPN uses for its base, in other words, it's symmetrical (Vcb = Veb) and has high breakdown (Veb = Vcb = 30V or so). This is handy for differential inputs, where you might put 30V across them in saturation.

There are plenty of circuits that work nicely at low hFE. Current mirrors are the major use of PNP, just to supply a little bias current to the NPN stuff (diff amp loading, volt amps, bandgap references, etc.). hFE is low, so higher order mirrors are common (the kind with the "darlington"-esque boosted input end, Wilson mirrors, etc.), and low bias currents are common (you don't want to waste 1mA base current for every

2-3mA circuit you supply, but fortunately you don't need more than a few uA, since these are *tiny* transistors and they'll run fast, even at low currents).

You'll never(??) see lateral PNPs as emitter followers or open collector outputs in ICs, since those would consume huge base currents, even if darlingtoned a stage or two. If hFE = 3, a triple darlington would only get you a total of 27 gain, while dropping over two Vbe's -- you'll get much better performance from a weak PNP pull-up (maybe 10uA) and an NPN follower (hFE = 200 gives Imax ~ 2mA), with a dropout of just over one Vbe, or an NPN darlington to increase the current to "who gives a crap" levels (>200mA, geometry limited by then). Now the dropout is two Vbe's, but the available current is huge, and the current efficiency is high (you're only wasting the 10uA pullup). Op-amps, the 555 timer, even the stepper motor driver L298 (2A output capacity) use this type of output stage. (TTL logic does not, because they didn't use lateral PNP; instead, a resistor provides the internal pull-up.)

Now, if epitaxy is used, or ion implantation, one has essentially unlimited control over doping -- you aren't limited by trying to overdope an existing layer, so you could, for instance, put high voltage collectors on top of high gain base-emitter junctions, in either polarity. You're still limited on mask cost, so you'll want to optimize one type (almost always NPN), and you can always fall back on using the lateral technique in a pinch.

Tim

--
Deep Friar: a very philosophical monk.
Website: http://webpages.charter.net/dawill/tmoranwms
Reply to
Tim Williams

Yep. A good engineer quickly learns to first look at the author's name. If that is Jim Williams, Bob Pease, Robert Widlar, Dean Banerjee or one of the other gurus I know it's good stuff.

--
Regards, Joerg

http://www.analogconsultants.com/
Reply to
Joerg

Tim, that was a very good break down. You may find this hard to believe but I actually understood that, being that I am a back hill Maine cow herder.

It would explain the reason I see the use of PNP on some designs being frown on and needed in others due to their low hfe states.

What i've found is that PNP's seem to have a high failure rate, mostly in the loss of hfe and some times open in the base. I think some where I read once it was a process issue that caused the problem with some PNP devices.

As for the latch up, I thought that problem for the most part was relevant in CMOS only? Due to how the CMOS is done, a thyristor bipolar body is naturally formed as part of the CMOS design and there for will trigger if gate for example exceeds Vdd > .7. Maybe I got my ducks mixed up, but what ever.

Years ago, we modified a design that used CMOS chips and one of them would go into a latch now and then and burn the chip before it was noticed, most of the time. The reason for this was external and hard to control. So we put in a thyristor circuit of our own that would trigger if this CMOS circuit did go into a latch and reverse bias, a current source that was supplying Vdd. There was also an LED placed on the panel for indication. It served to save the CMOS chip and show the event that took place. We later on did find out what was causing over input but left it that way because we used that as a control feature :)

Remember, it is feature not a bug!

Jamie

Reply to
Jamie

Oh boy, you know how to get brownie points. Was there something a mystery you've been working on lately? I am sure one of those guys will charm right in now :)

Jamie

Reply to
Jamie

"Jamie" wrote in message news:jCHLq.11599$ snipped-for-privacy@newsfe11.iad...

Failure has many causes, excess heat, breakdown, those sorts of things, but they are all aggravated by impurities. Excess doping (a 5-layer PNP) would have lots of impurities, so much that I would think it would be fairly useless. Epitaxial PNP might be acceptable (freedom in voltage ratings and current gain, high speed), but because epitaxy is a deposition process, it has more dislocations than substrate silicon. The impurities and dislocations usually increase speed (more "recombination centers" for spare electrons and holes to get stuck on and reunite through), but they also worsen those other properties.

The question, are monolithic PNP as reliable as NPN on a complementary process, I would expect NPN are given priority on process refinements, because they perform slightly better and deserve those refinements. Even if they are made equal, the slightly poorer performance (higher Vce(sat), or lower gain, allowing the NPN to desaturate the PNP) may cause it to fail first. But a much wider answer would have to ask in return, what circuit is it in? Often, a PNP is added where required, and the rest handled in NPN; this makes very asymmetrical circuits when it comes to balanced outputs. Even with equal transistor parameters, a quasi-complementary output stage might simply be driven with more pull-up current than pull-down, causing the PNP to dominate under fault conditions.

I might be mistaken as well. It's my recollection that NPNs are made with an N-well (the collector) embedded in a P-substrate, and putting two more junctions on top of that necessarily makes a four layer device.

It is worth noting that a regular thyristor goes PN-PN, where the first junction is forward-biased by the anode voltage, the second is reverse biased (making the common collector region between the PNP and NPN effective sections) and the third one by the gate (under user control). When a thyristor is reverse-biased, it goes P-NPN and nothing can happen, because even if the NPN is turned on, the top P-N junction is reverse-biased, requiring charge to diffuse all the way across the (wide, lightly doped) middle N region. This current is going to be weak -- the NPN essentially has a collector on its collector, and most of the charge recombines in the first before any can reach the second. I would expect leakage current to increase (I should try this and see), but it obviously won't remain on.

To get the thyristor into an active form, the NPN collector would have to be brought below substrate (i.e., ground), which would activate the substrate PNP as well. This would be a pretty darn good way to activate it, and inductive loads on outputs would easily achieve this.

Lateral PNP are intended primarily to send current sideways, but (depending on the thickness of the N-well), they should work just dandy producing substrate current as well, although without latchup (they could induce latchup in nearby transistors due to the substrate current).

For these two reasons, I expect they go to great lengths -- deep N-wells, guard rings, that sort of stuff -- to prevent latchup in bipolar circuits.

Now, as for CMOS, it has the same sort of structures (now NPN and PNP structures are always lateral, and both N- and P-wells are required), but under normal operation, it's all nice and clean, signals stay within the rails, no minority carriers to splash around, wells can be as shallow as you want. But if you need a robust process, you still need all those space-hogging features that bipolar requires by default. On the upside, it's great for LSI/VLSI, because you can reasonably assume all your low level internal circuitry isn't going to be bothered by any of the nasty outside world. The result, of course, is a sizable fraction of die area committed to pin structures (input protection diodes and isolation, output transistors and latchup protection), while a microscopic blob of logic provides the functionality.

Tim

--
Deep Friar: a very philosophical monk.
Website: http://webpages.charter.net/dawill/tmoranwms
Reply to
Tim Williams

interesting.

I don't know if you were here in the past when I had a strange batch of smt 2222's that exhibited what looked like self oscillation when testing them in a basic common emitter circuit with a high side R as the load? If You carefully advance the base bias and keep a watch on the collect, there was a point you would see a burp in voltage at the collector. Playing with the bias, I could keep it there.

So, I was able to use the older Lecroy scope we had to took a delayed, widen snap shot of that area. It was actually an oscillation taking place but it was only ~50mv p-p. Moving the bias up/down or waiting for beta to change due to tempco, would put this out of scope.

We did these test because this lot was used in a 0..1 volt inverter stage to another section and found it not to behaving correctly.

We tried various configs and it did not matter, other than putting a heavy cap on the collector, which that wasn't going to work for us.

Dampening the base with a heavy cap only reduced it a small portion but did not fix it.

We ended up getting another 100 of these units from our supplier after we explained the issue, they didn't have any problems replacing them. I kind of think that maybe I wasn't the only one? On top of that, they are kind of cheap any way.

The replacements were perfect.

P.S. These units worked fine in a switching state, just not in linear mode at a precise current state.

Jamie

Reply to
Jamie

e
n

Jim Williams, Bob Pease and Robert Widlar are dead, Bob Widlar for some years now.

Dan Banerjee still seems to be with us, but since he works for National Semiconductor, Joerg probably doesn't authorise enough parts per year to qualify for his interest.

You seem to be even more out of touch with reality than Jim Thopmson, who does still seem to know about electronics gurus, presumably because he's yet to lose contact with the realities of electronics.

-- Bill Sloman, Nijmegen

Reply to
Bill Sloman

^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ Bill, you're in constant denial. You wish you had a tenth of inclination Jim has, even at is current age.

Jamie

Reply to
Jamie

CMOS doesn't have to be twin tub.

Most companies want latch-up trigger current to be above 100ma. Certainly about 40ma. So you really need to abuse the chip to get it to latch. Often current limiting resistors will do the job.

Reply to
miso

Now, now! I'm about to celebrate only my 18th birthday in 2012 ;-) ...Jim Thompson

--
| James E.Thompson, CTO                            |    mens     |
| Analog Innovations, Inc.                         |     et      |
 Click to see the full signature
Reply to
Jim Thompson

You and your premature conclusions :-)

Dean actually answered one of the more unorthodox inquiries I had in person. National impressed the heck out of me when he did, that was good customer service. Bob Pease did, too, by the way. The only company that could rival that in my cases is Linear Technology, and back in the old days Analog Devices.

So what kinds of products have you designed lately? Say, last year?

--
Regards, Joerg

http://www.analogconsultants.com/
Reply to
Joerg

e

er.

ot

are

e on

e.

ne

l

Have you been spending time with John Larkin? Whenever I correct one of his nonsense off-topic posts, he tries to get back at me by asking that question.

The answer is - as you well know - none. The Dutch electronics industry is of the opinion that anybody over 55 ought to retire and that anybody over 65 is retired, and I'm 69, so I'm retired, whether I like it or not. I don't - as I mention here from time to time - but I don't have the contacts or the attitude necessary to set up a consulting business of my own, so I'm stuck with it. You've give me good advice on the subject which I'd need a personality transplant to be able to follow - I'm grateful for it, but it's not advice I'm equipped to exploit.

I'm still fooling around with my variant on the Baxandall Class-D oscillator, but have yet to get beyond LTspice into gEDA to create a schematic of a circuit that I could build. I should probably talk to my GP about anti-depressants, but can't be bothered ...

-- Bill Sloman, Nijmegen

Reply to
Bill Sloman

That another thing I started but am not making any progress on. I've got print-out of all my weekly reports - nominally directed to my bosses but actually circulated to the whole project team - for the three years of the electron beam tester project at Cambridge Instruments (the one which featured Gigabit Logics GaAs logic clocked at 800MHz for the coarse timing).

formatting link

I've scanned in - and edited - the first six months worth, but can't be bothered getting on with getting through the rest.

-- Bill Sloman, Nijmegen

Reply to
Bill Sloman

Yeah, I keep forgetting to ask mine about my memory problems...

Seriously, I know depression is no joke.

You don't at all need to make a PCB, just a soldering iron and a piece of copper-clad FR4 is all I use for most circuits like that. Or even do it Jim Williams / Jan style "air wiring".

--

John Devereux
Reply to
John Devereux

ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here. All logos and trade names are the property of their respective owners.