Can you damage an LCD by inverting an image at the same rate as the 'M' signal?

IIRC, the 'M' signal alternates (with every frame?) to reverse the voltage across pixels to prevent a DC bias damaging the pixels (by some electrolytic effect?).

I can see this works for a static image, but what would happen if you had the screen being inverted at exactly the same rate?

Would this result in a net DC bias and ensuing damage?

Or does M spend 50% of the time in each state for each line of pixels?

A mate of mine reports 'screen burn' on some LCD monitors at work. I thought that only happened in older CRTs. Perhaps 'M' wasn't exactly 50% duty cycle for those LCDs.

K.

Reply to
Kryten
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Interesting...

But I don't think this is possible because the image "pixels" cannot be updated faster than the frame rate, while the M signal is typically faster than this (to avoid flicker).

For example, on some QVGA(320x240) STN LCDs I am working with, the M signal is the "line sync" (LP) pulse divided by 16.

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John Devereux
Reply to
John Devereux

So over 32 lines, M would be 50% high, 50% low. Hmm, 240/16=15 so M would alternate between frames also.

Would I be right to think this is only going to guarantee 50% duty cycle if either

a. Each frame

or

b. Each group of 32 lines

is driven twice with the same data.

Each pixel will only experience the alternating M signal over two frames.

I suspect that LCDs drive one line at a time (or two for dual-scan).

Therefore M ought to alternate over the course of each line.

Looking at one LCD data sheet, it shows an internal M generator clocked by FLM and LP, which suggests M alternates slower than the line rate.

It is possible to flip all pixels at the frame rate (e.g. set start-of-screen pointer to an all-black image or an all-white image). This would undo the effect of M.

I'd be curious to see if this can damage a screen, though not so much as to try it with my expensive new laptop! :-)

Reply to
Kryten

From:

formatting link

"3d6h index 5Eh (R/W): ACDCLK Control Register (82c455/6/7, 655x0 only) bit 0-6 ACDCLK Count. Number of Hsync pulses between changes in ACDCLK. 7 If set the ACDCLK phase inverts every frame, if clear the ACDCLK changes phase when the number of Hsync pulses specified in bits 0-6 have elapsed."

This indicates that M (aka ACDCLK) alternates at half the frame rate at most, and one 64th the frame rate at least.

This only has the effect of alternating between odd and even frames.

They only used 16 as a divisor because the number of lines divides to an odd number, and it only needs a 4-bit counter.

240 divided by 2, 4 or 8 yields an even number, so they could not use those.

All they really needed was to halve the FLM rate.

Reply to
Kryten

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