Boost Converter Efficiency Improvements

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I need to generate approx. 200V at 20mA from a 12V supply.

My first attempt is a multiplying SEPIC (i.e. the 2nd inductor is
connected to the output of the first stage, instead of ground).
It's working reasonably well but I'd like to improve the efficiency.

I'm getting 80% efficiency at the moment which is acceptable but I'm
sure it could be better.

I'm using a couple of 100uH inductors which are nowhere near  
saturation (1.4A peak and they're rated for 3.4A). They have quite a  
low DCR, around 130mR, and I doubt I can get much lower than that  
cheaply. They settle at around 40 Celcius.

The inductors are joined with a large 1uF PET film cap (EPCOS  
B32562J3105K). Is this the best type?

The FET (A D2PAK with no PCB heatsink area) is slightly cooler than  
that, around 35C. The gate is driven from 12V with an 85ns rise time  
and a 170ns fall time. It's just a few transistors driving the gate,  
not a driver IC. As the FET is cool, is there much efficiency to be  
gained by improving the drive speed?

I'm driving this at 40kHz, from a processor PWM so I can't really  
increase the frequency much.

The two diodes Schottkys, so they should be fast enough

The output electrolytic (4u7 @ 400V) gets to around 40C as well. I  
could use several to lower the ESR but would that give a better  
overall efficiency?

I appreciate the obvious solution might be a transformer, but I'd like
to get the most out of what I've got for now.


Dave.

Re: Boost Converter Efficiency Improvements
David Jordan wrote:
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So 4W, not a whole lot. But 12V to 200V is quite ambitious.


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At 4W that means your total losses have to be well under 800mW. Very
feasible but now you have to look in every nook and cranny.


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250mW peak loss just from the DC resistance, too much. You need
inductors with lower DCR.

40C mean they are either tiny or you also have RF losses in the core. So
you may need a lower loss core as well.


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Yikes! 170nsec is an eternity for a switcher designer. Either drive the
driving transistors with more gusto or, better yet, us a real gate
driver chip. TC or MC series, for example. And gate resistors are only
for wimps :-)


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At 40W that's ok. But 100uH doesn't sound like much for a 200V supply at
40kHz. Also, try not to drop this below 40kHz because it could drive
animals nuts. They'll hear the magnetostrictive buzz.


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Sure? Schottkies are generally <100V, above that you may need SiC.
Schottkies above 100V are usually big old fat ones, probably too much
capacitance for your low power application.


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40C in the cap is not good at all. Get a better one or hang several 1uF
in parallel, and also make sure there is a 0.1uF/250V ceramic in parallel.


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12V -> 200V is a strrrrretch but can be done. If you want >80% in such a
low power case you've got to look at all the stuff meantioned above. No
stone can be left unturned.

--  
Regards, Joerg

http://www.analogconsultants.com/

Re: Boost Converter Efficiency Improvements
wrote:

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It might be a little higher in the end, 220V @ 25mA. I've tried this  
on the existing design and I still get the same 80% efficiency so I'm
happy there's enough wiggle room for later changes.

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And there're two of them... The 2nd one is only around 1A peak though.

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They're a Coilcraft MSS1210-104KEB, 12mm square and 10mm high and  
shielded. It was the lowest DCR I could easily find in a smallish SMD.

It looks like the next step up would be a leaded toroid at around 80mR
or an SMD toroid at 32mR but an enormous 25mm diameter, and around  
twice the price.  

I'll get some to experiment with and see how much difference they  
make, I can solder them to the existing pads to test.

To be honest, I wasn't really considering RF losses. I didn't think  
they'd be significant at 40kHz.

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I'm driving the gate with an emitter follower plus a few other parts  
for level shifting with, of course, no gate resistor :)
I tried tweaking a few resistor values to speed up the transition, I  
shaved off a few mA but nothing really significant. The current you  
save improving the efficiency of the FET is lost in the driver.

I do have a 15V zener on the gate but that should be <100pF.

It looks like a TC1411 should give me rise/fall times of around 40ns.
An MCP1407 would lower this to 20ns. And they're the same pinout...

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I picked this value as it gave a ~40% duty cycle and a reasonable peak
current.  

I'm not too happy about the 40kHz but using the processor PWM has a  
few advantages, I can do a soft start for example and alter the output
voltage in software. I also get a very low power 'OFF' state. I don't  
need a fast loop response so it looked like a good fit.

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They're Vishay VSSB420S, 200V 4A (Cj of 120pF). Over-specced and  
expensive. I was thinking of just using an ES1J, much cheaper and a Cj
of 8pF.

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I do have a ceramic on there, a 1206 100nF.

I just measured a 3.2ohn ESR on one of those caps. That won't be  
helping any.

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Thanks for you help, I've got a few things to try.


Dave.


Re: Boost Converter Efficiency Improvements
David Jordan wrote:
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[...]


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Yeah, I see your predicament. Another option is to increase the
frequency but for that you'd need an external oscillator outside your
uC. Or see if you can trick the uC by using a timer and let the loop
alter the CC register on the fly.


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But there have to be some. Because the Coilcraft lists 2.5A for a 20C
rise. Your average current is maybe a 1/5th of that, yet you still see a
20C rise. Since you are in the UK and the weather wasn't that great
lately in Europe I assume ambient was 20C or less :-)


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If that is the case then the FET may be oversized. If you use one with a
very fat gate capacitance that can result in a penalty. With a 20:1
step-up ratio there is always a penalty. The Miller feedback is a real
issue.


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Those would definitely be a step in the right direction. 170nsec
turn-off time are really painful here, much more so than any turn-on
time. Even if you used your transistor scheme, if you could have a
snappier path to zero that would help. Or maybe if you could even pull
negative, that helps a ton.


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40% duty cycle? That has me confused, normally it would be much more
extreme.

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But you should also be able to do that with one of then timers in there,
hoping it has one. The off state current would also be very low. Your
loop would have to set values in a CC register.


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Yikes. Those are monsters, way too big, too much capacitance:

http://www.vishay.com/docs/89317/vssb420s.pdf


I was thinking of just using an ES1J, much cheaper and a Cj
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Mucho mejor. No Schottky but at 35nsec I think they could be snappy enough.

http://www.mccsemi.com/up_pdf/ES1A-L~ES1J-L (DO-214AC).pdf


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Ouch. But electrolytics in that capacitance and voltage range will
always be around that value. I never use electrolytics on switchers if I
can help it. And of course no tantalums either. TDK has 2.2uF/250V in
2220 size, but they are over a buck a pop. This type is usually still
the better deal:

http://www.digikey.com/product-detail/en/GRM55DR72E105KW01L/490-3550-2-ND/789398
http://www.digikey.com/product-detail/en/C5750X7R2E105K230KA/445-2304-2-ND/789698


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You are welcome. Getting the FET to turn off in well under 100nsec will
go a long way here.

--  
Regards, Joerg

http://www.analogconsultants.com/

Re: Boost Converter Efficiency Improvements
wrote:

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It's looking like I'll have to do something similar to that anyway. I  
have a PWM period of 100 and altering the duty cycle by 1 gives a  
change in output voltage of 2-3V. To get better than 1% regulation  
I'll need to dither the duty cycle.

I've got plenty of CPU horsepower available so I was thinking of a  
slowish loop to set the gross output voltage and a fast loop to just  
increment / decrement the duty cycle by 1 as needed depending on if  
the output is below / above the setpoint.

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We've had a few days of sun here so it's more like a 15C rise :)  
That's still FAR too high though. The losses from the DC resistance  
are going to be around 50mW so I'd expect only a couple of degrees  
rise.

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<SNIP>

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It is over-sized, it's a Vishay SUM33N20-60P-E3, 33A 200V. I wanted  
low on resistance. As it doesn't get very warm, and it'll be cooler  
still if I drive the gate harder, I'm looking at something like an  
IRF7820. There are 150V FETs but there's not much cost saving and 150V
is a bit close for comfort.

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I think I've settled on using a proper gate driver now. It takes the  
same board space as the collection of transistors and resistors I'm  
using now but will be much better.  

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Have a look a the schematic I posted elsewhere in this thread. I  
picked the multiplying SEPIC topology specifically so I would have a  
sensible ~50% duty cycle rather than a 90%+ one. It makes things a lot
more controllable and it keeps the peak voltage down on the FET and
diodes.

<SNIP>

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I swapped the Schottkys for ES1Js. It made no significant difference  
to the overall efficiency, <1%. They're much cheaper though so that's  
a win.

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Hey, that's a coincidence! I put that exact part on order earlier this
morning. LTSpice shows one of those by itself would give lower ripple  
than the 4u7 elctrolytic. Doesn't X7R give you roughly 50% the rated  
capacitance at the rated voltage though? I think I'll put two on the  
PCB to make sure.

<SNIP>

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Yes, I think the plan for the next revision is:
- Proper gate driver IC
- Swap the output electrolytics for ceramics
- Different inductors (tricky, all the alternatives are huge)


I like the look of John Larkin's design, using a dual inductor as a
kind of autotransformer. I've ordered some parts for that as well as I
want to see how well it performs in reality.


Dave.


Re: Boost Converter Efficiency Improvements
David Jordan wrote:
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Looks like you've only got a 4MHz clock on the uC then.


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Or do a McGyver:

Run the timer CC register output into several port pins with series
resistors connected to them in R2R fashion. Those resistors would all
tie into a capacitor. A qualifier determines which ones will be set and
this qualifier would become the "vernier adjust" in your loop. Run this
through a comparator of your uC in order to square it up. Three port
pins would already increase the granularity by a factor of eight.

Then you could also up the switcher frequency. Plus it can keep copycats
 at bay. They'd wonder "Now how on earth does this work?".


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Sure looks like RF core losses then.


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The 1750pF gate capacitance is also a bit high. Costs drive energy.

http://www.irf.com/product-info/datasheets/data/irf7820pbf.pdf


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But keep the gate capacitance low, meaning don't oversize the FET. There
is always a sweet spot between Rdson losses and gate drive related
losses. The latter would encompass losses in the gate driver itself but,
more importantly, also linear-mode losses because the transitions become
longer.


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Yes, you are right. But it burns a lot of power in C1. I'd consider
ceramics at least for that cap.


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Every fraction of a percent counts :-)


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http://www.digikey.com/product-detail/en/GRM55DR72E105KW01L/490-3550-2-ND/789398
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http://www.digikey.com/product-detail/en/C5750X7R2E105K230KA/445-2304-2-ND/789698
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The higher density X7R can easily lose 50% capacitance. Manufacturers
tend to not put that in the datasheets, maybe because it doesn't look
good. But usually you can get that number from their support engineers.
Main thing is, you really don't want the high ESR of an electrolytic, at
least not for C1.


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The DC resistance is ok, you just have to find a kind with less core
losses. Since datasheets are typically lacking in that domain the only
way to find out is often to contact the mfg's support engineers or try
out a lot of inductors.

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If that still isn't good enough maybe get a flyback transformer. They
are ubiquitous and cheap these days.

--  
Regards, Joerg

http://www.analogconsultants.com/

Re: Boost Converter Efficiency Improvements
wrote:

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<SNIP>

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It's a PIC24 at 8MHz so the timers run at 4MHz. I can increase to
clock speed if I have to but only to 32MHz which would give 4 times
the current resolution.

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I think I see where you're going with this. This would be a 0-250ns  
delay to the start of the output pulse. The Rs and Cs would have to be
chosen depending on the PWM frequency.

The FET would be driven from the comparator output. The OC pin(s)  
would go high, the cap would start to charge at a variable rate until  
the comparator switches and drives the FET on after a delay.  
When the OC pin(s) go low, I'd have to discharge the cap quickly via a
diode so there's no delay turning off.

I can use the PPS functionality to map the OC output to multiple pins  
as well.

Sneaky. I like it!

It's also easy to bypass in software if it turns out to be *too*  
sneaky. Just remap the pin driving the FET back to the raw OC output  
instead of the comparator output.

The only thing to look out for is, for example, the transition between
27+(7/8) to 28+(0/8). I'd have to do this at the right time to avoid a
single pulse of 27+(0/8) or 28+(7/8).

<SNIP>

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I've just stuck on a couple of big (40mm) toroids that I found in my  
junk box and the efficiency is now 86%. Unfortunately I have no idea  
what the core material is!

So, yes, at *least* 350mW is core losses in the inductors.

With the DC losses, I think >400mW split between the two inductors  
could explain the 15C rise.

Now the difficult bit. How to identify a 'low-loss' inductor.

Is a higher SRF better? It suggests a lower winding capacitance which  
may help.

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I've found an FQD18N20, 830pF typical. It's 140mR though so it'll burn
around 120mW.

The Miller feedback is certainly significant at the moment, the flat  
spot in the slope is around 70ns wide.

<SNIP>

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I've ordered a selection of inductors, I'll try that first. For the  
core material, most datasheets just say 'Ferrite' which is really  
helpful!

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This simple little switcher is turning out to be quite interesting.

Many thanks to everyone for your advice so far.


Dave.

Re: Boost Converter Efficiency Improvements
David Jordan wrote:
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[...]


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That could possibly even be auto-calibrated by the uC. It could monitor
the output voltage and find out "Whoops, it's not supposed to jump here"
and then truncate the 7/8th step.


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But now you know that a lion's share of the losses is indeed core
losses. In the end you'll probably have to try a lot, assuming you must
live with catalog inductors. Or contact a good vendor. Wuerth would be
one of them on your side of the pond.


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Yes, it sure does.


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Unfortunately not. Absent any datasheet info it's as difficult as
picking a horse at the races. Best bet is to approach manufacturers and
tell them you want to operate a SEPIC around 40kHz, and which of their
inductors would be the least in core losses. The reason is that they
won't tell you where they buy their core materials.


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And that's where the FET goes linear. If you have to push efficiency to
the max you'll have to find the sweet spot in the compromise between
Rdson and capacitances. In your case Cgd is very important. I usually
get a lot of models and try it on SPICE. It's always a bit of a pain
when such a job needs to be done in summer because then the PC drives
the office temperature way up. For Saturday the forecast says 43C ...


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Yup. That's like saying "contains barley" :-)


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Those are great learning experiences because now you get face-to-face
with every loss contributor in the switcher. The next design will then
become so much easier.

--  
Regards, Joerg

http://www.analogconsultants.com/

Re: Boost Converter Efficiency Improvements
On Wednesday, June 5, 2013 6:49:45 PM UTC+2, Joerg wrote:
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[snip]

Sounds intriguing, but don't you need to add a ramp to the comparator then or
how do you get that CC value converter to 3 more bits?
  
Regards

Klaus

Re: Boost Converter Efficiency Improvements
On Wednesday, June 5, 2013 11:25:46 PM UTC+2, Klaus Kragelund wrote:
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So
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how do you get that CC value converter to 3 more bits?
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Please disregard this post, Dave explained it nicely, didn't know the meaning of
vernier, now do :-)

Very nice trick. Microcontroller comparators are often quite slow and has large
VOS, but since this is in a closed loop, the slowness will only set minimum duty
cycle as the delay is just an offset of the loop duty cycle.

Regards

Klaus

Re: Boost Converter Efficiency Improvements
Klaus Kragelund wrote:
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[...]

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I have the same kind of aha situations when reading documentation in
Spanish :-)


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But every time I suggest something like this the firmware guys throw
stuff at me. Because they are the ones who have to implement it.


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There is another variant of this trick: Use only the one CC register
output directly and go into the comparator via a fixed RC. If you don't
want to sacrifice an OC port pin you can use a diode to discharge the
cap quickly in the other direction.

Then use a 2nd timer for PWM, RC filter that as well with a much larger
time constant and use this to feed the other comparator input. Then the
SW loop only has to adjust a duty cycle, which moves the comparator
threshold.

--  
Regards, Joerg

http://www.analogconsultants.com/

Re: Boost Converter Efficiency Improvements
wrote:

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<SNIP>

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This is looking even better now! The PIC I'm using has a 16-step  
adjustable reference for the internal comparators so possibly only a  
single RC (with a diode across the R) may be needed.

You can select a voltage from 0-66% of VDD.

I'll have to breadboard it just to try this out.


Dave.

Re: Boost Converter Efficiency Improvements
David Jordan wrote:
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Cool. You might need another resistor across the cap to keep it in this
0-66% band.


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However, to make this successful for a production run you have to solve
the newly introduced problem that you mentioned, the 15/16th to 0/16th
step, without resorting to precision caps and stuff. Note that I bit my
tongue and didn't say "... but that's just software" :-)

--  
Regards, Joerg

http://www.analogconsultants.com/

Re: Boost Converter Efficiency Improvements
wrote:

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It's not too slow. 25ns delay on the rising edge, 35ns on the falling
edge.

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I wasn't able to use all 16 steps, the lower 3 were useless because of
the slope of the discharge at the falling edge. I've thrown away the  
top 5 to give 8 reasonably linear steps (and it makes the software  
easier).

With a 250ns period, I need a value of 0-7 to give a delay of  
0-218.75ns to the rising edge of the pulse.

With a 1K65 and a 220pF, and a BAT85 across the 1K65, I get:

Value    Delay (ns)
0         13
1         44
2         72
3        100
4        130
5        161
6        193
7        226

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I need to change the duty cycle and the comparator reference while the
output's low.

I can just map an interrupt input to the pin that's assigned the  
comparator output, set to trigger on a falling edge (once, when I want
to update the period). With a maximum 50% duty cycle, I'll have at  
around 12.5us to change the values, plenty of time.

An extra 3 bits of resolution for 'free'!

I was hoping to find the reference settling time in the datasheet but  
no, it'd listed as 'TBD'.


Dave.


Re: Boost Converter Efficiency Improvements
David Jordan wrote:
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[...]


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That looks very decent.


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Yay! That's always a good feeling. A free lunch after all :-)


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Might be a good thing to ask their application engineers. With uC I
found that manufacturers sometimes have data that hasn't made it into
the datasheet because they thought it wasn't urgently needed. Even with
lowly device like zener diodes I was often able to get min-max data from
their own QC at currents much lower than spec'd.

--  
Regards, Joerg

http://www.analogconsultants.com/

Re: Boost Converter Efficiency Improvements
On Wednesday, June 5, 2013 6:49:45 PM UTC+2, Joerg wrote:
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Couldn't you use a digital input instead of the comparator, since the positive
threshold of the digital input will be constant over short time?  

Cheers

Klaus

Re: Boost Converter Efficiency Improvements
Klaus Kragelund wrote:
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Yes, you could. But then you'd be operating outside spec and some uCs
will start drawing extra current when an input hovers around VCC/2. The
1st pair in there is then in the linear range, which result in cross
current. If you have a 5V uc and run that at full voltage it can be
significant.

Not that I haven't use logic chips in linear mode ...

--  
Regards, Joerg

http://www.analogconsultants.com/

Re: Boost Converter Efficiency Improvements
On 6/5/2013 10:48 AM, David Jordan wrote:

[Snip]

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http://www.digikey.com/product-detail/en/GRM55DR72E105KW01L/490-3550-2-ND/789398
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http://www.digikey.com/product-detail/en/C5750X7R2E105K230KA/445-2304-2-ND/789698
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That cap has a DF of .025 at 1kHz. That would be about .85 ohms at 1kHz.
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TDK has some high-voltage, high-capacitance (for ceramic, anyway) parts.  
They have DF <= 1%. Not cheap, though. Look on Mouser.

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How much output ripple can you stand?

Re: Boost Converter Efficiency Improvements
wrote:

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http://www.digikey.com/product-detail/en/GRM55DR72E105KW01L/490-3550-2-ND/789398
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http://www.digikey.com/product-detail/en/C5750X7R2E105K230KA/445-2304-2-ND/789698
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<SNIP>

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<SNIP>

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The current version with its electrolytics is OK in that respect so
somewhere around the 1% level is good.

The 4u7 electrolytics at 3R2 give a 2Vp-p ripple. A 500nF (if it drops
that much) at 850mR gives a 1Vp-p ripple so it's certainly no worse  
and the losses should be much lower.


Dave.


Re: Boost Converter Efficiency Improvements
"David Jordan"  wrote in message  

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I just tried your simulation, and by changing C1 and C3 to 1uF ceramics  
with  
25mOhm ESR the efficiency jumped from about 85% to over 97%. There was  
about  
500 mW of heat in the electrolytics. I haven't followed all of this  
thread  
but I built a similar boost converter for nominal 12VDC to about 60VDC  
at  
nearly 50 watts, on a board about 1" wide by 2.5" long, for a high power  
13  
LED diving flashlight. I couldn't get much better than 85% efficiency,  
especially when the battery voltage sagged to 10.5. I was using a  
PIC16HV616  
with PWM up to 200 kHz, but best results were about 50 kHz. I used a  
single  
inductor boost topology.

Good luck!

Paul  


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