Binary counter - please check my work

Why not just use the three LSb's of the counter "as is"and inverting the most significant of those (with your NAND gate) to form the MSb (of four)?

+1

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Rick C

it's easier to get the first column by inverting the secondd.

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Ah, indeed, indeed.

DUH.

This is why I ask...;-)

There are no "steady state" consequences of this. However, the temporal behavior of the "4th bit" will vary near the clock edge as it will be more closely synchronized with the other three bits in the case where the state is set-up *before* the clock edge vs. derived from the TRANSITIONED third bit AFTER the clock edge.

?

The 74HC163 data sheet is defective.

shows, in its application section, the use of the ripple carry output of th e first counter in a string as a "look-ahead carry" for the rest of the cou nters.

The 160,161,162 and 163 synchronous counters were ground-breakers in offeri ng this, which meant that while an eight-bit counter couldn't count as fast as a four bit counter, any counter of a higher multiple of four bits could be just as fast as the eight-bit counter.

Some counter designers were a bit slow to wake up to this.

Sloman A.W. ?Comment on ?Modular digital box-car for applic ations in pulsed laser spectroscopy? Review of Scientific Instrumen ts, 67 3763-4 (1996)

It isn't the only fault that I savaged in that comment, but it was one of t hem. I'd picked up the same fault when acting as referee on a paper some te n years earlier, and that paper got published showing a rather different co unter than the one I'd criticised.

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Bill Sloman, Sydney

It looked to me like the only sequence of transitions where one can get a set of unique bit patterns where some two bits can be ANDed or ORed together to get 8 mutually exclusive "1" outputs where the output is "0" in all the other states.

But I believe I'm wrong. 4 choose 0 + 4 choose 1 is only 5.

"El Cheapo" 2 switch sample and hold is my ideal, but I don't know that it's possible:

Better to use a SPDT type to switch the summing-node input current to ground, see AoE III, pages 916-919 and Figure 13.47. Current steering with no voltage changes on the three switch terminals. I learned that trick from the HP / Agilent Master Designers.

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 Thanks, 
    - Win

Yep, I was going for something like that...The input to the multiplexer is being driven from this little IC that takes an analog input and spits out 7 band-passed and peak detected control voltages:

As usual I'm not using it for its intended purpose - I need to pretty accurately sample and hold these control voltages while the strobe pulses to its clock input cycles around.

What I have drawn there I don't think will work, at least with the

4051...the 4051 only has one input and 8 outputs but for a dual switching arrangement inside the feedback loop it looks like each channel needs switches that don't share poles.

So it's get a better switch IC and/or back to the drawing board.

How is that a peak detect?

The signal to be de-multiplexed coming in from the left will already be peak-detected; I just need to hold a positive DC value.

for

"8 mutually exclusive "1" outputs where the output is "0" in all the other states."

use

CD4022 (counter)

or

74xx328 (3-bit decoder)

etc.

CD4022 may power up in a confused state with 2 outputs high, but a reset pulse or few clocks will cure that.

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I'm not totally sure what is being requested, but would a Johnson ring counter do the job? The mutually exclusive 1 outputs is what this type of counter is all about. It would use a 4 bit shift register, an inverter and some logic to detect the various combinations of 10 and 01 adjacent bits.

I can't find any info on a 74xx328 device. Did you mean a 74xx138 which is a 3 bit to 8 output decoder?

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Rick C

Is this being used to drive a bar graph display or something? If so you're stuck in the 1980s, almost nobody uses an analog S/H for stuff like this anymore. An A/D is the ultimate S/H, and you don't need a lot of precision for a display, an 6-bit will do.

Nope, not going to be used to drive a display (though that's what the manufacturer intended), I'm experimenting with using the outputs to feed the control voltage inputs of a set of VCAs.

An input signal gets passed thru a set of switched-capacitor bandpass filters (like the MF10) with VCAs hung on the outputs. Modulator gets sent to the display filter, then the outputs are held and fed to the VCAs. Then you have a vocoder, no uP required.

A little compander chip like the SA571 on the carrier signal input and expander on the output could help reject clock noise. I was thinking if I'm clever a 4 bit counter fed from a stable clock at a high frequency should be able to provide all the required clocks to drive the filterbanks, switch the S&H switches, and feed the display filter IC's clock as well.

How is that supposed to work with random music?

Which part? An array of bandpass filters whose outputs are peak-detected and converted to control voltages that track the amplitudes of each band of the modulator, which are fed to VCAs that are fed by bandpassed bins of the carrier centered around the same frequencies is exactly how an analog vocoder works for any kind of signals.

I think companding the carrier to achieve noise reduction should work by using a compressor gain element section in a feedback rather than feedforward config - prior to the switched capacitor filters/VCAs, but with the level detector input fed post processing/clock residual. Then expanded after the detector.