battery-backed SRAM

I'm designing a benchtop gadget that will uses a 7020 ZINQ SOC chip, which is an FPGA with two ARM cores on-chip. I want to save a user's last setup when power fails, and restore it at powerup. The 7020 has on-chip batter-backed ram, but apparently only to store some encryption key, not for general use. So I need an external ram and a battery.

Digikey offers exactly 4000 choices when I do a search for SPI interfaced SRAM. None of the few that I've looked at mention the battery interface, specifically whether how to ensure data integrity and low Vcc current through the power fail. I've done the powerdown interface logic myself in the past, for parallel SRAMs, but it's a nuisance.

Anybody know of a serial SRAM that includes the battery/powerdown bits?

I need less than a kilobyte of storage for the current setup. We could SPI out the setup every few seconds. Maybe pingpong two or so copies with checksums, in case power dies in the middle of a write.

I guess we could use serial flash, but write endurance is an issue. Maybe a huge (like 128 Mbit) serial flash, with thousands of copies of the setup, would make more sense than an SRAM and a battery. Some algorithm, run at powerup, could find the most recent valid setup image. 100K write cycles seems to be a common spec, which is scary.

I could write the setup only if it changes, on the theory that most of the time nobody is twiddling knobs. That would improve endurance.

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John Larkin         Highland Technology, Inc 

lunatic fringe electronics
Reply to
John Larkin
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Solve all your problems simultaneously: look for FeRAM. It's available serial and parallel, in all sizes.

It can be operated (R/W cycle) more times than the chip can see in its lifetime.

TI even makes MSPs with the stuff onboard!

Tim

-- Seven Transistor Labs, LLC Electrical Engineering Consultation and Contract Design Website:

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Reply to
Tim Williams

Had a similar problem years ago with limited write cycles on a serial EEPRO M. The 'solution' on that one was to start a timer when a control was chang ed and keep resetting the timer while controls changed. 60 seconds after th e last change it used a write cycle. Of course you have 60 seconds of possi ble loss of the settings if a power failure happens.

Reply to
stratus46

There is, or at least used to be, NVRAM, needs no battery... in the days of my interest ~40 years ago at OmniComp/GenRad, was used to store cash register (NCR) data in case of power failure.

(I actually didn't "use" the NVRAM, NCR had me design a tester for NVRAM that would insure that the parts were good. They came back whining a month after the first breadboard was submitted for their evaluation that it didn't work... turned out that it worked very well, their NVRAM was bad >:-} ...Jim Thompson

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Reply to
Jim Thompson

That's interesting.

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Available, affordable, 1e10 write cycles. We could still rotate a few copies of the setup, in case anything goes wrong.

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John Larkin         Highland Technology, Inc 

lunatic fringe electronics
Reply to
John Larkin

Why is that scary? If this is a manual setup situation, you are set (worst case) for three setups per day for the next 90 years.

And, that's not a 'write cycle' when you store your 100 bytes of setup, it's only a 'write cycle' when you fill 32kbytes with setup records, and start rewriting over the old blocks. CAT32C256

is cheaper than a battery and socket, rated for 1M operations.

1M x 32k / 100 = about 300 million setup-store operations

The chip is hugely oversized, in this case, for the records you are storing, and isn't erased each time. Append a serial-number to each setup, and at startup time scan for the highest serial number.

Reply to
whit3rd

What do you see as missing from this one:

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It seems terse but complete to me -- don't let the battery input go below

1V or above 3.6V, and expect it to maybe go over to battery power when VCC gets below 2V, and definitely if it gets below 1.6V.
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Tim Wescott 
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Reply to
Tim Wescott

You might take a look at the super capacitors. 1 farad will buy you about

10 days/volt at 1 micro amp. Then write 3 copies when something's changed and use 2 matching versions on power up.

Hul

John Lark> I'm designing a benchtop gadget that will uses a 7020 ZINQ SOC chip,

Reply to
Hul Tytus

FRAM (Tim beat me to it...).

1e14 r/w cycles, 150 yr retention @ 65*C:
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Cheers, James Arthur

Reply to
dagmargoodboat

That's nice; the battery switch stuff is built in. But it's sounding like the fram parts are better... no battery required.

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John Larkin         Highland Technology, Inc 

lunatic fringe electronics
Reply to
John Larkin

Is your equipment expected to last longer than that?

Vbat support

Some how the Battery replacement seems more professional for high quality gear. Cheers

Reply to
Martin Riddle

I designed some in when I was fresh out of school. They certainly seemed to work at the time.

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Tim Wescott 
Control systems, embedded software and circuit design 
I'm looking for work!  See my website if you're interested 
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Reply to
Tim Wescott

MRAM. New and allegedly improved replacement for FeRAM. Sorry, but no personal exprience with either FeRAM or MRAM.

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Reply to
Jeff Liebermann

What's wrong with EEPROM?

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Reply to
TTman

Speed and, usually more importantly, there is a lifetime maxaximum number of write cycles.

Reply to
krw

In the 1980s, many cartridges for the original 6502-based Nintendo Entertainment System used battery backed SRAM for save game states.

I plugged in my old copy of The Legend of Zelda a couple years ago, and all my saved games from when I were a kid were still there, just as I had left them.

The last time I played the game was around 1989.

Reply to
bitrex

If we had a power fail during a write, the saved setup could be corrupted. May as well save a few copies with checksums.

100K write endurance might be a problem. 1e10 certainly will not.

Batteries are big and expensive. An SO8 serial nvram is ideal.

--

John Larkin         Highland Technology, Inc 

lunatic fringe electronics
Reply to
John Larkin

But this is about a procedure only done occasionally (manual change of settings, or cold power-up), so speed doesn't matter. A hundred bytes, plus overhead, at 400 kHz serial, only takes a few milliseconds.

It's not 'write', but 'erase' that matters. A change of settings DOES write, but it isn't a 'write cycle' because you can make hundreds to thousands of records before anything has to be erased. It's limited how many erasures can be done before error rate bites ya.

Reply to
whit3rd

But then you need complicated wear-leveling methods. By far the most common technique will be: reading and writing (where "write" means "unconditional erase of these bytes, followed by writing the bits needed") a constant range of addresses, covering the offset and size of the struct being recorded.

It's definitely not something you can do for logging purposes (say, recording a timer or event counter, every update, so that no data is lost on power-down), not for any length of time. That's historically where NVRAM* was used (RTCs and such), and it's precisely where FRAM and MRAM fit today.

*Well, there used to be core. Anyone who had experience with it, do you know if it was treated as RAM (i.e., wiped and polled and checked for patterns, on POST) or if some/all was reserved for NV purposes? Did programs make any assumptions about NVity?

Tim

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Seven Transistor Labs, LLC 
Electrical Engineering Consultation and Contract Design 
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Reply to
Tim Williams

Also batteries are subject to arbitrary and ever-changing transport restrictions, e.g. after various laptop fires, many couriers here won't take (or charge extra to take) equipement containing coin cells, even though they were considered fine since the 80's or before, and the laptop / hoverboard batteries that cought fire were totally different kinds of battery.

Reply to
Chris Jones

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