We think this batch of boards is unacceptable. The board vendor disagrees, or is at least vague. I think we'll send them back.
This house is usually excellent, but every PCB maker seems to lose the recipe sooner or later.
-- John Larkin Highland Technology, Inc picosecond timing precision measurement jlarkin att highlandtechnology dott com http://www.highlandtechnology.com
Den fredag den 20. maj 2016 kl. 23.35.47 UTC+2 skrev John Larkin:
borderline but I think as long as the within the pad it should work, I'd assume that is why they have a spec for minimum annular ring
are those pads with minimum annular ring?
-Lasse
The concern isn't so much the ring being off-center, as it's the seriously reduced effective trace widths at the entry to the vias.
-- John Larkin Highland Technology, Inc picosecond timing precision measurement jlarkin att highlandtechnology dott com http://www.highlandtechnology.com
Check against IPC specs...definitive answer
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On the last 2 pictures, ALL of the drill holes appear to be off in the same direction. This seems to be an error in aligning the drilled panels with the phototool for the expose/develop/etch step.
The first picture seems to show only one hole out of position.
If you have done a bunch of work with them, they ought to be willing to redo them, as the last two pictures do seem to show a number of holes nearly drilling through the annular ring.
Jon
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wouldn't that only be an issue if the via plating is substantially thinner than the track thickness?
even with zero annular ring the track still transition directly into at least a track width of via plating
imagine a road going through a tunnel
-Lasse
What id, od?
Does your drawing or .TXT have a minimum annular ring, breakout, hole positional tolerance, etc. spec?
The trace width isn't necking down, the copper is dropping down the hole. Plating inside the barrel is usually thinner, but there's about pi more of it. It's also surrounded by FR4 fibers, whereas outside traces have air on one side.
Tim
-- Seven Transistor Labs, LLC Electrical Engineering Consultation and Contract Design Website:
What was the spec for non-dimensioned holes?
Cheers
IPC-6012 is the qualification document.
Cheers
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I've used MIL-P-55110 when a customer has required it. I notice that it is now deprecated in favour of MIL?PRF?31032.
Regards, Allan
The edge of the top hole in the last pic is almost smashed right through the surrounding solder mask. I'm no PCB expert but I'd say...reject reject reject
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I get this from the dirt cheap Chinese vendors. I assume the drill bit is dull and the holes are wandering. I try to use a larger annular ring when possible.
I had a batch of boards about like John's once. I was told they met IPC class 2 specs which I had been quoted. Looks like John's boards are not so good. 3.5.1 of IPC-6012B says the minimum trace width should be 80% of the specified width and the "Land/Conductor Junction" should not be less than that. The only question is whether both remaining bits are added together when the hole is centered on the trace entry. The illustration in the document shows a hole off center with one corner cut off completely. But even adding the two bits together likely still aren't 80% of the specified trace width.
I think on my board the hole misalignment was at about 45 degrees to the routing so none of the traces were separated from the pads like these are.
-- Rick C
Those are pretty awful, especially the last one.
What other dimensions are off, besides the clearly visible hole placement?
Maybe I'm misinterpreting the IPC spec, but according to Table 3-5, the Class 2 breakout is allowed to be up to 90 degrees (see Figure 3-2). JL's had no breakout at all.
You *are* misinterpreting the spec by not reading it fully. If the breakout exceeds 90 degrees it is bad. But it can also be bad by restricting the width of the contact of trace to pad to less than the allowed width of the trace which is 80% of the trace width specified. A breakout is not required to fail. I think they spec this because the pad is essential to distributing the current around the via circumfrence. We get used to thinking of perfect holes and perfect plating, but it can be very irregular inside the hole. So the current needs to be distributed to get good conductivity.
The boards I had some years ago had holes right up to the edge of the pad but not outside I believe. Even so, the traces were all at 90 degree angles and the hole registration was off on a 45 degree angle, so the offset didn't impact the connection of the trace and the pad.
I wonder if designers consider the 80% factor when sizing traces for power? By the IPC spec the entire trace can be 80% of what it is intended to be and pass.
-- Rick C
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