Audio Sampling Question

Hi All,

I'm sampling high-fidelity analog audio at 44.1 kHz with a 16-bit ADC. The analog audio is noise-free for the purposes of this question.

The ADC data stream goes to a microprocessor that compares the data in blocks of multiple samples to a previously stored set of data. When the ADC output data matches the stored data, the microprocessor generates an output pulse. Some amount of processing time "X" is needed to recognize a match and generate the pulse.

My question, again assuming zero analog noise, is: what is the time uncertainty of the output pulse? In other words, if I split the same analog audio into two of these circuits in parallel, how much could their output pulses differ in time? Is the answer simply the clock frequency accuracy?

Thanks is advance.

Reply to
Henry VIII
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What method is being used th compare the data to the previously stored set?

Reply to
Richard Henry

I'm not expert but I do know that some ADC's are several clocks behind in there samples.

Reply to
Jon Slaughter

No, it depends on how well the analog front ends of the ADCs are matched. If the matching isn't near perfect, you'll have different phase shifts.

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Reply to nico@nctdevpuntnl (punt=.)
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Reply to
Nico Coesel

There are several possible sources of variation. How bad each one is depends on your hardware and possibly on the nature of the signal.

Are the analog filters identical? A slight difference in phase shift will introduce an error. Even if you use the same analog input and compare measurements at different times there could be variations due to temperature.

Are the ADCs on a common clock? If they use two different clock sources there could be an error of up to half the sample rate.

Does the microprocessor have any other tasks that could delay it getting a sample?

How do you define "matches the data?" No ADC is perfectly repeatable when the input signal is right on the edge of two digital output values.

Finally, why the "assuming zero analog noise" simplification? how about the many other ways such a system is imperfect?

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Guy Macon
Reply to
Guy Macon

The 'compare' operation can do more than just set a bit; you can measure the time delay (phase shift) due to the sampling clock being asynchronous to the input signal, and your microprocessor can know exactly how long to delay its 'recognize' signal output. So the jitter is the microprocessor time-slice (not necessarily the same as a single clock cycle).

If your operation is a simple comparison, the 44 kHz clock can be up to +1/2 cycle or down to - 1/2 cycle different from the reference case, so the jitter would be related to the sample clock.

And, of course, some signals (like a steady sine wave) would trigger an output once per cycle, so a single 'match' can result in thousands of outputs; the uncertainty there is very large (they are all true matches, but only one is 'right' in some targeted sense).

Reply to
whit3rd

The

ADC

output

Assuming randomlike signal

dT = q /(sqrt(T * Fs) *Slew)

q - quantization step T - signal duration Fs - sample rate Slew - average slew rate

Vladimir Vassilevsky DSP and Mixed Signal Consultant

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Reply to
Vladimir Vassilevsky

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