Asynchronous reset in "master-slave" D flip-flop

Hello,

I'm trying to build a D flip-flop from gates using the "master-slave" design, but I can't figure out how to implement an asynchronous reset. Does anyone have any idea how this is done? I can't seem to find any circuit designs online, just a bunch of HDL code.

Thanks a ton for your help!

Reply to
round daworld
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The asynchronous reset (preset) is simply another connection to the cross-coupled pairs to force them into the state you want independent of the state of the clock.

Reply to
krw

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http://focus.ti.com/lit/ds/symlink/sn74ls74a.pdf
Reply to
John Fields

If you follow this you'll find a layout and some help on how to generate a schematic for it:

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Basically a set/reset path is implemented with a gate in the path of the feedback to set a value regardless of the clock state.

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Muzaffer Kal

DSPIA INC.
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Reply to
Muzaffer Kal

Maybe try reading your textbook with a bit more depth...

Reply to
Fred Bloggs

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