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Astable multivibrator with MOSFET SPICE model

Could some electronics guru point me to a working(i.e., correctly simulates) astable multivibrator SPICE model with MOSFET only. I have two working BJT based astable multivibrator SPICE models. However, my MOSFET based astable multivibrator model, works as per hand calculation, but shows no oscillations with a regular SPICE .TRAN analysis. I have tried the standard SPICE tricks, as having voltage pulses on some nodes to kick start the oscillations, but these have no effect. Any hints, suggestions would be greatly appreciated. Thanks in advance.

Reply to
dakupoto
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Post your schematic. The usual transistor astable won't work if you just drop in mosfets.

--

John Larkin         Highland Technology, Inc 

lunatic fringe electronics
Reply to
John Larkin

Post your schematic file (.ASC) ...Jim Thompson

--
| James E.Thompson                                 |    mens     | 
| Analog Innovations                               |     et      | 
| Analog/Mixed-Signal ASIC's and Discrete Systems  |    manus    | 
| San Tan Valley, AZ 85142     Skype: skypeanalog  |             | 
| Voice:(480)460-2350  Fax: Available upon request |  Brass Rat  | 
| E-mail Icon at http://www.analog-innovations.com |    1962     | 
              
I love to cook with wine.     Sometimes I even put it in the food.
Reply to
Jim Thompson

Usually setting a nonzero voltage as an initial condition on the timing capacitor will start it up...

Reply to
bloggs.fredbloggs.fred

Unless both mosfets settle down to saturated.

We need to see his circuit.

--

John Larkin         Highland Technology, Inc 

lunatic fringe electronics
Reply to
John Larkin

They will settle both on. The culprit is that there is no path for the timing capacitor charging current on the gate side when the gate is high. A MOS differs from a bipolar transistor or JFET (and also a tube) that there is no current via the gate when the transistor is turned fully on.

The following thing works. The charge path is via diodes D7 and D8 in the Basic version. The price to pay is that the transistors do not turn fully on.

Version 4 SHEET 1 1104 1448 WIRE -160 -176 -256 -176 WIRE -16 -176 -160 -176 WIRE 304 -176 -16 -176 WIRE 464 -176 304 -176 WIRE 768 -176 464 -176 WIRE -16 -144 -16 -176 WIRE 768 -144 768 -176 WIRE -16 -16 -16 -64 WIRE 48 -16 -16 -16 WIRE 192 -16 112 -16 WIRE 560 -16 192 -16 WIRE 640 -16 560 -16 WIRE 768 -16 768 -64 WIRE 768 -16 704 -16 WIRE 192 16 192 -16 WIRE 304 16 304 -176 WIRE 464 16 464 -176 WIRE 560 16 560 -16 WIRE -256 160 -256 -176 WIRE -16 160 -16 -16 WIRE 48 160 -16 160 WIRE 192 160 192 96 WIRE 192 160 112 160 WIRE 352 160 192 160 WIRE 464 160 464 96 WIRE 464 160 416 160 WIRE 624 160 464 160 WIRE 768 160 768 -16 WIRE 768 160 688 160 WIRE 880 160 768 160 WIRE -16 256 -16 160 WIRE 48 256 -16 256 WIRE 304 256 304 96 WIRE 304 256 112 256 WIRE 352 256 304 256 WIRE 560 256 560 96 WIRE 560 256 416 256 WIRE 624 256 560 256 WIRE 768 256 768 160 WIRE 768 256 688 256 WIRE -16 304 -16 256 WIRE 768 304 768 256 WIRE 192 384 192 160 WIRE 192 384 32 384 WIRE 560 384 560 256 WIRE 720 384 560 384 WIRE 560 432 560 384 WIRE 608 432 560 432 WIRE -256 448 -256 240 WIRE -16 448 -16 400 WIRE 768 464 768 400 WIRE -160 848 -160 -176 WIRE 0 848 -160 848 WIRE 208 848 0 848 WIRE 576 848 208 848 WIRE 784 848 576 848 WIRE 0 880 0 848 WIRE 208 880 208 848 WIRE 576 880 576 848 WIRE 784 896 784 848 WIRE 0 1024 0 960 WIRE 64 1024 0 1024 WIRE 208 1024 208 960 WIRE 208 1024 128 1024 WIRE 368 1024 208 1024 WIRE 784 1024 784 976 WIRE 784 1024 432 1024 WIRE 896 1024 784 1024 WIRE 0 1120 0 1024 WIRE 368 1120 0 1120 WIRE 576 1120 576 960 WIRE 576 1120 432 1120 WIRE 640 1120 576 1120 WIRE 784 1120 784 1024 WIRE 784 1120 704 1120 WIRE 0 1168 0 1120 WIRE 784 1168 784 1120 WIRE 208 1248 208 1024 WIRE 208 1248 48 1248 WIRE 576 1248 576 1120 WIRE 736 1248 576 1248 WIRE 576 1296 576 1248 WIRE 624 1296 576 1296 WIRE 0 1312 0 1264 WIRE 784 1328 784 1264 FLAG 768 464 0 FLAG -16 448 0 FLAG -256 448 0 FLAG 608 432 g1 FLAG 880 160 Out1 IOPIN 880 160 Out FLAG 784 1328 0 FLAG 0 1312 0 FLAG 624 1296 g3 FLAG 896 1024 Out2 IOPIN 896 1024 Out SYMBOL nmos 720 304 R0 SYMATTR InstName M1 SYMATTR Value 2N7002 SYMBOL nmos 32 304 M0 SYMATTR InstName M2 SYMATTR Value 2N7002 SYMBOL res -32 -160 R0 SYMATTR InstName R1 SYMATTR Value 1k SYMBOL res 752 -160 R0 SYMATTR InstName R2 SYMATTR Value 1k SYMBOL res 176 0 R0 SYMATTR InstName R3 SYMATTR Value 100k SYMBOL res 544 0 R0 SYMATTR InstName R4 SYMATTR Value 100k SYMBOL diode 704 -32 R90 WINDOW 0 0 32 VBottom 2 WINDOW 3 32 32 VTop 2 SYMATTR InstName D1 SYMATTR Value 1N4148 SYMBOL diode 48 0 R270 WINDOW 0 32 32 VTop 2 WINDOW 3 0 32 VBottom 2 SYMATTR InstName D2 SYMATTR Value 1N4148 SYMBOL voltage -256 144 R0 SYMATTR InstName V1 SYMATTR Value 5 SYMBOL diode 624 272 R270 WINDOW 0 32 32 VTop 2 WINDOW 3 0 32 VBottom 2 SYMATTR InstName D3 SYMATTR Value 1N4148 SYMBOL diode 112 144 R90 WINDOW 0 0 32 VBottom 2 WINDOW 3 32 32 VTop 2 SYMATTR InstName D4 SYMATTR Value 1N4148 SYMBOL res 288 0 R0 SYMATTR InstName R5 SYMATTR Value 10k SYMBOL res 448 0 R0 SYMATTR InstName R6 SYMATTR Value 10k SYMBOL diode 624 176 R270 WINDOW 0 32 32 VTop 2 WINDOW 3 0 32 VBottom 2 SYMATTR InstName D5 SYMATTR Value 1N4148 SYMBOL diode 112 240 R90 WINDOW 0 0 32 VBottom 2 WINDOW 3 32 32 VTop 2 SYMATTR InstName D6 SYMATTR Value 1N4148 SYMBOL cap 416 144 R90 WINDOW 0 0 32 VBottom 2 WINDOW 3 32 32 VTop 2 SYMATTR InstName C1 SYMATTR Value 1n SYMBOL cap 416 240 R90 WINDOW 0 0 32 VBottom 2 WINDOW 3 32 32 VTop 2 SYMATTR InstName C2 SYMATTR Value 1n SYMBOL nmos 736 1168 R0 SYMATTR InstName M3 SYMATTR Value 2N7002 SYMBOL nmos 48 1168 M0 SYMATTR InstName M4 SYMATTR Value 2N7002 SYMBOL res -16 864 R0 SYMATTR InstName R7 SYMATTR Value 1k SYMBOL res 768 880 R0 SYMATTR InstName R8 SYMATTR Value 1k SYMBOL res 192 864 R0 SYMATTR InstName R9 SYMATTR Value 100k SYMBOL res 560 864 R0 SYMATTR InstName R10 SYMATTR Value 100k SYMBOL diode 640 1136 R270 WINDOW 0 32 32 VTop 2 WINDOW 3 0 32 VBottom 2 SYMATTR InstName D8 SYMATTR Value 1N4148 SYMBOL diode 128 1008 R90 WINDOW 0 0 32 VBottom 2 WINDOW 3 32 32 VTop 2 SYMATTR InstName D7 SYMATTR Value 1N4148 SYMBOL cap 432 1008 R90 WINDOW 0 0 32 VBottom 2 WINDOW 3 32 32 VTop 2 SYMATTR InstName C3 SYMATTR Value 1n SYMBOL cap 432 1104 R90 WINDOW 0 0 32 VBottom 2 WINDOW 3 32 32 VTop 2 SYMATTR InstName C4 SYMATTR Value 1n TEXT 304 368 Left 2 !.tran 1m TEXT 304 400 Left 2 !.ic V(g1)=3 TEXT 320 1264 Left 2 !.ic V(g3)=3 TEXT 288 736 Left 5 ;Basic TEXT 256 -280 Left 5 ;Complete RECTANGLE Normal -316 680 1096 1444 2 RECTANGLE Normal -320 564 1088 -360 2

--

-TV
Reply to
Tauno Voipio

On 29/01/16 17:54, John Larkin wrote:

Here are two that work. You won't like it.

Jeroen Belleman

=========================== Version 4 SHEET 1 1192 680 WIRE -80 -96 -272 -96 WIRE 96 -96 -80 -96 WIRE 240 -96 96 -96 WIRE 416 -96 240 -96 WIRE 864 -96 416 -96 WIRE 1088 -96 864 -96 WIRE -80 -64 -80 -96 WIRE 96 -64 96 -96 WIRE 240 -64 240 -96 WIRE 416 -64 416 -96 WIRE 864 -64 864 -96 WIRE 1088 -64 1088 -96 WIRE -272 32 -272 -96 WIRE 96 48 96 16 WIRE 112 48 96 48 WIRE 128 48 112 48 WIRE 240 48 240 16 WIRE 240 48 192 48 WIRE 768 64 704 64 WIRE 864 64 864 16 WIRE 864 64 848 64 WIRE 704 112 704 64 WIRE 944 112 704 112 WIRE 1040 112 1008 112 WIRE 1088 112 1088 16 WIRE 1088 112 1040 112 WIRE -80 128 -80 16 WIRE 128 128 -80 128 WIRE 384 128 192 128 WIRE 416 128 416 16 WIRE 416 128 384 128 WIRE 96 160 96 48 WIRE 416 160 416 128 WIRE 864 160 864 64 WIRE 992 160 864 160 WIRE 864 176 864 160 WIRE 1088 176 1088 112 WIRE -80 240 -80 128 WIRE -32 240 -80 240 WIRE 0 240 -32 240 WIRE 48 240 0 240 WIRE 240 240 240 48 WIRE 320 240 240 240 WIRE 368 240 320 240 WIRE 704 256 704 112 WIRE 752 256 704 256 WIRE 816 256 752 256 WIRE 992 256 992 160 WIRE 1040 256 992 256 WIRE -272 288 -272 112 WIRE 96 288 96 256 WIRE 416 288 416 256 WIRE 864 320 864 272 WIRE 1088 320 1088 272 WIRE 0 336 0 304 WIRE 0 336 -272 336 WIRE 320 336 320 304 WIRE 320 336 0 336 WIRE -272 352 -272 336 WIRE -272 448 -272 432 FLAG 96 288 0 FLAG -272 288 0 FLAG 416 288 0 FLAG -32 240 G1 FLAG 320 240 G2 FLAG 112 48 D1 FLAG 384 128 D2 FLAG -272 448 0 FLAG 1088 320 0 FLAG 864 320 0 FLAG 1040 112 D4 FLAG 752 256 G3 SYMBOL nmos 48 160 R0 SYMATTR InstName M1 SYMATTR Value 2N7002 SYMBOL res 80 -80 R0 SYMATTR InstName R1 SYMATTR Value 1k SYMBOL res -96 -80 R0 SYMATTR InstName R2 SYMATTR Value 100k SYMBOL voltage -272 16 R0 SYMATTR InstName V1 SYMATTR Value 10 SYMBOL nmos 368 160 R0 SYMATTR InstName M2 SYMATTR Value 2N7002 SYMBOL res 400 -80 R0 SYMATTR InstName R3 SYMATTR Value 1k SYMBOL res 224 -80 R0 SYMATTR InstName R4 SYMATTR Value 100k SYMBOL cap 192 112 R90 WINDOW 0 0 32 VBottom 2 WINDOW 3 32 32 VTop 2 SYMATTR InstName C1 SYMATTR Value 100n SYMBOL cap 192 32 R90 WINDOW 0 0 32 VBottom 2 WINDOW 3 32 32 VTop 2 SYMATTR InstName C2 SYMATTR Value 100n SYMBOL voltage -272 336 R0 SYMATTR InstName V2 SYMATTR Value 3 SYMBOL diode 304 240 R0 WINDOW 0 -33 66 Left 2 SYMATTR InstName D2 SYMBOL diode -16 240 R0 WINDOW 0 -40 61 Left 2 SYMATTR InstName D3 SYMBOL nmos 1040 176 R0 SYMATTR InstName M3 SYMATTR Value 2N7002 SYMBOL nmos 816 176 R0 SYMATTR InstName M4 SYMATTR Value 2N7002 SYMBOL res 1072 -80 R0 SYMATTR InstName R5 SYMATTR Value 1k SYMBOL res 848 -80 R0 SYMATTR InstName R6 SYMATTR Value 1k SYMBOL res 864 80 M270 WINDOW 0 32 56 VTop 2 WINDOW 3 0 56 VBottom 2 SYMATTR InstName R7 SYMATTR Value 100k SYMBOL cap 1008 96 R90 WINDOW 0 0 32 VBottom 2 WINDOW 3 32 32 VTop 2 SYMATTR InstName C3 SYMATTR Value 33n100n TEXT 88 376 Left 2 !.ic v(G1)=0 TEXT 48 -136 Left 2 !.tran 100m

Reply to
Jeroen Belleman

[Full Listing at Message-ID: ]
2nd version is clever... bias "class-A" guarantees starting (in real life, though .TRAN doesn't always self-start). ...Jim Thompson 
--
| James E.Thompson                                 |    mens     | 
| Analog Innovations                               |     et      | 
| Analog/Mixed-Signal ASIC's and Discrete Systems  |    manus    | 
| San Tan Valley, AZ 85142     Skype: skypeanalog  |             | 
| Voice:(480)460-2350  Fax: Available upon request |  Brass Rat  | 
| E-mail Icon at http://www.analog-innovations.com |    1962     | 
              
I love to cook with wine.     Sometimes I even put it in the food.
Reply to
Jim Thompson

[...]

The 2nd version more commonly done with logic inverters.

Jeroen Belleman

Reply to
Jeroen Belleman

Yep, I do that all the time. I usually do the 3-inverter version, with lots of snap and always starts. ...Jim Thompson

--
| James E.Thompson                                 |    mens     | 
| Analog Innovations                               |     et      | 
| Analog/Mixed-Signal ASIC's and Discrete Systems  |    manus    | 
| San Tan Valley, AZ 85142     Skype: skypeanalog  |             | 
| Voice:(480)460-2350  Fax: Available upon request |  Brass Rat  | 
| E-mail Icon at http://www.analog-innovations.com |    1962     | 
              
I love to cook with wine.     Sometimes I even put it in the food.
Reply to
Jim Thompson

On Fri, 29 Jan 2016 22:39:36 +0100, Jeroen Belleman wrote:

This works, and doesn't need any more parts than the one that doesn't work.

Version 4 SHEET 1 1192 680 WIRE 96 -96 -272 -96 WIRE 416 -96 96 -96 WIRE 96 -64 96 -96 WIRE 416 -64 416 -96 WIRE -272 32 -272 -96 WIRE -32 48 -80 48 WIRE 64 48 48 48 WIRE 96 48 96 16 WIRE 96 48 64 48 WIRE 128 48 96 48 WIRE 240 48 192 48 WIRE 288 48 240 48 WIRE 416 48 416 16 WIRE 416 48 368 48 WIRE -80 128 -80 48 WIRE 128 128 -80 128 WIRE 384 128 192 128 WIRE 416 128 416 48 WIRE 416 128 384 128 WIRE 96 160 96 48 WIRE 416 160 416 128 WIRE -80 240 -80 128 WIRE -32 240 -80 240 WIRE 48 240 -32 240 WIRE 240 240 240 48 WIRE 320 240 240 240 WIRE 368 240 320 240 WIRE -272 288 -272 112 WIRE 96 288 96 256 WIRE 416 288 416 256 FLAG 96 288 0 FLAG -272 288 0 FLAG 416 288 0 FLAG -32 240 G1 FLAG 320 240 G2 FLAG 384 128 D2 FLAG 64 48 D1 SYMBOL nmos 48 160 R0 WINDOW 0 -21 105 Left 2 WINDOW 3 63 105 Left 2 SYMATTR InstName M1 SYMATTR Value 2N7002 SYMBOL res 80 -80 R0 WINDOW 0 -52 28 Left 2 WINDOW 3 -54 58 Left 2 SYMATTR InstName R1 SYMATTR Value 1K SYMBOL res 64 32 R90 WINDOW 0 63 47 VBottom 2 WINDOW 3 62 49 VTop 2 SYMATTR InstName R2 SYMATTR Value 100k SYMBOL voltage -272 16 R0 WINDOW 0 60 38 Left 2 WINDOW 3 62 73 Left 2 SYMATTR InstName V1 SYMATTR Value 10 SYMBOL nmos 368 160 R0 WINDOW 0 -5 109 Left 2 WINDOW 3 61 106 Left 2 SYMATTR InstName M2 SYMATTR Value 2N7002 SYMBOL res 400 -80 R0 WINDOW 0 54 35 Left 2 WINDOW 3 57 66 Left 2 SYMATTR InstName R3 SYMATTR Value 1k SYMBOL res 384 32 R90 WINDOW 0 -47 54 VBottom 2 WINDOW 3 -42 54 VTop 2 SYMATTR InstName R4 SYMATTR Value 99k SYMBOL cap 192 112 R90 WINDOW 0 74 29 VBottom 2 WINDOW 3 78 29 VTop 2 SYMATTR InstName C1 SYMATTR Value 100n SYMBOL cap 192 32 R90 WINDOW 0 -40 32 VBottom 2 WINDOW 3 -38 30 VTop 2 SYMATTR InstName C2 SYMATTR Value 100n TEXT 520 112 Left 2 !.tran 100m uic TEXT 552 32 Left 2 ;Async TEXT 496 72 Left 2 ;JL Jan 29, 2016

--

John Larkin         Highland Technology, Inc 

lunatic fringe electronics
Reply to
John Larkin

I think you have hit the nail on the head. As I do not use LTSpice, but Ngspice, could you please post your netlist in the form of my own netlist (please see below):

.INCLUDE powerirfmodels

.SUBCKT NICAP 1 2

  • 1 IN
  • 2 OUT C0 1 3 10.0u L_ESL 3 4 5.0nH R_ESR 4 2 1.2 .ENDS

VDD 1 0 DC 5.0 AC 0.0 XC0 4 3 NICAP XC1 2 5 NICAP XC2 5 0 NICAP XM0 2 3 0 irf530n XM1 4 5 0 irf530n R0 1 2 100 R1 1 3 2.0K R2 3 0 0.5K R4 1 4 100 R5 1 5 2.0K R6 5 0 0.5K

.OPTIONS NOPAGE METHOD=GEAR .IC V(2)=5 V(3)=2.0 V(4)=0.5 V(5)=2.5 .PROBE .TRAN 50.0us 5.0ms 10.0us UIC .PRINT TRAN V(2) V(4) .END

*** POWER MOSFETS

.SUBCKT irf530n 1 2 3

  • Node 1 -> Drain
  • Node 2 -> Gate
  • Node 3 -> Source

M1 9 7 8 8 MM L=100u W=100u .MODEL MM NMOS(LEVEL=1 IS=1e-32 VTO=3.79209 LAMBDA=3.64034 KP=81.097 CGSO=8.9e-06 CGDO=1e-11)

RS 8 3 0.056205 D1 3 1 MD .MODEL MD D(IS=9.06112e-12 RS=0.00982324 N=1.13042 BV=100 IBV=0.00025 EG=1.2 XTI=3.54513 TT=0.0001 CJO=7.4e-10 VJ=1.52632 M=0.693198 FC=0.5)

RDS 3 1 1e+06 RD 9 1 0.0219755 RG 2 7 4.4648 D2 4 5 MD1

  • Default values used in MD1:
  • RS=0 EG=1.11 XTI=3.0 TT=0
  • BV=infinite IBV=1mA .MODEL MD1 D(IS=1e-32 N=50 CJO=9.44672e-10 VJ=0.5 M=0.9 FC=1e-08)

D3 0 5 MD2

  • Default values used in MD2:
  • EG=1.11 XTI=3.0 TT=0 CJO=0
  • BV=infinite IBV=1mA .MODEL MD2 D(IS=1e-10 N=0.400249 RS=3e-06) ; RL 5 10 1)

GI2 7 9 4 0 VFI2 4 0 0 EV16 10 0 9 7 1 C0 11 10 1.29816e-09 GI1 7 9 11 6 VFI1 11 6 0 R_CAP 6 10 1 D4 0 6 MD3

  • Default values used in MD3:
  • Default values used in MD3:
  • EG=1.11 XTI=3.0 TT=0 CJO=0
  • RS=0 BV=infinite IBV=1mA .MODEL MD3 D(IS=1e-10 N=0.400249) .ENDS irf530n

.MODEL IRFZ34 NMOS(LEVEL=3 Gamma=0.0 Delta=0.0 Eta=0.0 Theta=0.0 Kappa=0.2 Vmax=0.0 Xj=0.0 Tox=100.0E-9 Uo=600 Phi=0.6 Rs=38.1E-3 Kp=20.42E-6 Vto=3.247 Rd=3.031E-3 Cbd=2.887E-9 Pb=0.8 Mj=0.5 Fc=0.5 Cgso=472.1E-12 Cgdo=292.8E-12 Is=1.981E-12 )

.SUBCKT irfz44n 1 2 3

  • Node 1 -> Drain
  • Node 2 -> Gate
  • Node 3 -> Source
.MODEL MM NMOS(LEVEL=1 IS=1e-32 VTO=3.56214 LAMBDA=0 KP=39.3974 CGSO=1.25255e-05 CGDO=2.2826e-07) .MODEL MD D(IS=9.64635e-13 RS=0.00967689 N=1.01377 BV=55 IBV=0.00025 EG=1.08658 XTI=2.9994 TT=1e-07 CJO=1.39353e-09 VJ=0.5 M=0.42532 FC=0.5) .MODEL MD1 D(IS=1e-32 N=50 CJO=1.52875e-09 VJ=0.5 M=0.584414 FC=1e-08) .MODEL MD2 D(IS=1e-10 N=0.408752 RS=3e-06) .MODEL MD3 D (IS=1e-10 N=0.408752) M1 9 7 8 8 MM L=100u W=100u RS 8 3 0.0133305 D1 3 1 MD RDS 3 1 2.2e+06 RD 9 1 0.0001 RG 2 7 2.20235 D2 4 5 MD1 D3 0 5 MD2
  • Default values used in MD2:
  • EG=1.11 XTI=3.0 TT=0 CJO=0
  • BV=infinite IBV=1mA RL 5 10 1 FI2 7 9 VFI2 -1 VFI2 4 0 0 EV16 10 0 9 7 1 CAP 11 10 2.06741e-09 FI1 7 9 VFI1 -1 VFI1 11 6 0 RCAP 6 10 1 D4 0 6 MD3 .ENDS
Reply to
dakupoto

Hope this is OK:

  • /Users/tauno/Desktop/ltspice/mosmv.asc M1 Out1 g1 0 0 2N7002 M2 N002 N004 0 0 2N7002 R1 N001 N002 1k R2 N001 Out1 1k R3 N003 N004 100k R4 N003 g1 100k D1 Out1 N003 1N4148 D2 N002 N003 1N4148 V1 N001 0 5 D3 g1 Out1 1N4148 D4 N004 N002 1N4148 R5 N001 N006 10k R6 N001 N005 10k D5 N005 Out1 1N4148 D6 N006 N002 1N4148 C1 N005 N004 1n C2 g1 N006 1n M3 Out2 g3 0 0 2N7002 M4 N007 N008 0 0 2N7002 R7 N001 N007 1k R8 N001 Out2 1k R9 N001 N008 100k R10 N001 g3 100k D8 g3 Out2 1N4148 D7 N008 N007 1N4148 C3 Out2 N008 1n C4 g3 N007 1n .model D D .lib /Users/tauno/Library/Application Support/LTspice/lib/cmp/standard.dio .model NMOS NMOS .model PMOS PMOS .lib /Users/tauno/Library/Application Support/LTspice/lib/cmp/standard.mos .tran 1m .ic V(g1)=3 .ic V(g3)=3
  • Basic
  • Complete .backanno .end
--

-TV
Reply to
Tauno Voipio

Here is one more, the classic emitter-coupled astable migrated to MOS. The output is not logic levels and not too beautiful, but the thing starts without kicking.

Version 4 SHEET 1 880 680 WIRE 256 -32 -128 -32 WIRE 640 -32 256 -32 WIRE 256 32 256 -32 WIRE 640 32 640 -32 WIRE 640 160 640 112 WIRE 640 160 96 160 WIRE 768 160 640 160 WIRE 256 208 256 112 WIRE 448 208 256 208 WIRE 256 240 256 208 WIRE 640 240 640 160 WIRE -128 304 -128 -32 WIRE 96 320 96 160 WIRE 208 320 96 320 WIRE 448 320 448 208 WIRE 592 320 448 320 WIRE 256 400 256 336 WIRE 416 400 256 400 WIRE 640 400 640 336 WIRE 640 400 480 400 WIRE 256 432 256 400 WIRE 640 432 640 400 WIRE -128 592 -128 384 WIRE 256 592 256 512 WIRE 640 592 640 512 FLAG 256 592 0 FLAG 640 592 0 FLAG -128 592 0 FLAG 768 160 Out IOPIN 768 160 Out SYMBOL nmos 592 240 R0 SYMATTR InstName M1 SYMATTR Value 2N7002 SYMBOL nmos 208 240 R0 SYMATTR InstName M2 SYMATTR Value 2N7002 SYMBOL res 240 16 R0 SYMATTR InstName R1 SYMATTR Value 1k SYMBOL res 624 16 R0 SYMATTR InstName R2 SYMATTR Value 1k SYMBOL res 240 416 R0 SYMATTR InstName R3 SYMATTR Value 4.7k SYMBOL res 624 416 R0 SYMATTR InstName R4 SYMATTR Value 4.7k SYMBOL voltage -128 288 R0 SYMATTR InstName V1 SYMATTR Value 5 SYMBOL cap 480 384 R90 WINDOW 0 0 32 VBottom 2 WINDOW 3 32 32 VTop 2 SYMATTR InstName C1 SYMATTR Value 10n TEXT -16 520 Left 2 !.tran 2m

--

-TV
Reply to
Tauno Voipio

Class-A on both sides, yet full 10V swing.

--
 Thanks, 
    - Win
Reply to
Winfield Hill

Once it gets going, it's almost the same as the classic circuit. Which, with mosfets, is still pretty bad.

The frequency will depend on gate thresholds, so will be pretty inaccurate, much worse than the NPN classic.

The dual NPN astable can seize up, just like the mosfet version, but usually doesn't. One has to be careful to not zener the NPNs, too.

--

John Larkin         Highland Technology, Inc 

lunatic fringe electronics
Reply to
John Larkin

Thanks a lot -- your netlist, with some minor editing, works fine with both HSpice and Ngspice.

Reply to
dakupoto

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