I need a family of S/H parts that has a VERY narrow aperture, but holds for a very long time.
At these rates, need 22-24 bit HOLD ability. Translates to 0.05ppm droop type hold.
Checked with TI, Analog Devices, and Linear, no luck.
Anybody done a 'roll your own'?
Not many people make s/h chips nowadays.
Sounds impossible to me. Some basic charge numbers look bad.
The best s/h circuits are internal to ADC chips, and the best around is something like the LTC2378-20, 20 bits with over 300 ns step response. Roughly 200:1 worse than what you need.
Sampling oscilloscope circuits have sub-100pS sampling gates, and infinite hold, but nowhere close to 22 bits accuracy. A 200 MHz streaming ADC will get you 16 bits these days.
People do compound s/h circuits to leverage aperature and droop. I've done a couple, and it's messy. But 5 ns and 22 bits is intimidating.
What's the application? Any other way to do this?
-- John Larkin Highland Technology, Inc picosecond timing precision measurement jlarkin att highlandtechnology dott com http://www.highlandtechnology.com
On the home page of my website, 4ns aperture time...
3,643,110 Sample and Hold Circuit PDFI don't know if it's made anymore, but something like that cascaded with a longer aperture/hold ?? ...Jim Thompson
--
| James E.Thompson | mens |
| Analog Innovations | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| San Tan Valley, AZ 85142 Skype: skypeanalog | |
| Voice:(480)460-2350 Fax: Available upon request | Brass Rat |
| E-mail Icon at http://www.analog-innovations.com | 1962 |
I love to cook with wine. Sometimes I even put it in the food.
Perhaps two follow and hold circuits in parallel with a simple switch would make more sense. Avoids the sampling issue, anyways.
RL
With those specs be prepared to shell out big bucks. You might want to think about a totally different solution for the job at hand because charge injection will be your enemy here.
That looks like an application for 2-3 S&H circuits in a row. So that each only needs a ratio of 10-30 between hold time and sampling window size.
-- Regards, Joerg http://www.analogconsultants.com/
The patent says "50 ns charging time", and that's charging, not settling to 8 bits. It's a 1 usec system. And the OP wants 22 bits.
Degree of difficulty ratio ~~ (2^22/5e-9) / (2^8/1e-7) = 3.3e5
22 bits in a fast analog s/h is probably impossible. The cap charging current is limited, so the cap has to be small, and at 22 bit levels, the charge injection error will need to be just a few dozen electrons.So I think it's impossible. Somebody is welcome to prove me wrong somehow.
-- John Larkin Highland Technology, Inc picosecond timing precision measurement jlarkin att highlandtechnology dott com http://www.highlandtechnology.com
I figure the charge injection error needs to be under 100 electrons. DC offsets can be cal'd out, but charge injection tends to be a nonlinear function of signal level and temperature. High performance s/h circuits are a bear to design.
We haven't even discussed aperature jitter. 5 ns and 22 bits requires roughly 1 fs jitter.
-- John Larkin Highland Technology, Inc picosecond timing precision measurement jlarkin att highlandtechnology dott com http://www.highlandtechnology.com
Each electron needs to file an application for a visa before entering the gate area, in triplicate.
-- Regards, Joerg http://www.analogconsultants.com/
Well, you could use cheaper, undocumented electrons. Don't be so negative!
Another issue: a 5 ns s/h has an analog bandwidth in the ballpark of
100 MHz. A 50 ohm resistor has 9 microvolts RMS of Johnson noise in 100 MHz bandwidth. Assuming a 5 volt signal, that's 2 PPM noise, about 19 bits s/n ratio. And it would be hard to get a real-world signal that good.So three problems:
Building a s/h that good
Aperature jitter
Inherent signal noise
-- John Larkin Highland Technology, Inc picosecond timing laser drivers and controllers jlarkin att highlandtechnology dott com http://www.highlandtechnology.com
Good catch, inherent noise is already taken into account.
Will double check, but aperture jitter is also taken into account.
Just need the value to 'hold' for a long time, or another way to word it,
if not 5uS, how long can I hold the signal for?
If the sampling problem can be solved,the droop is easy - output of first s/h is sampled with a second,slower one that has the required hold specs.
Worth adding, it may be worthwhile to consider trimming bad time constants. Namely: you can wait as long as you like, and apply time- and history-dependent correction (gain adjustment, absorption correction) to get it back. Good luck tuning it to ppm's though.
Tim
-- Seven Transistor Labs Electrical Engineering Consultation Website: http://seventransistorlabs.com
Interesting suggestion. Might be possible after using a 'calibration' mode. Don't hold much hope for the temp coefficient to repeat performance. Plus, the best I've been able to do in 'practical designs' is to improve
100X in onesy's, 10X in 'adjusted runs' and only around 3X in open Production. But 3X is 3X improvement and when it comes to noise...any improvement is an improvement.
Crazy idea: What about using an active discrete delay line? Input signal travels down the discrete delay line; each tap drives emitter of grounded base transistor; far end terminated. Transistor collectors drive taps in the output discrete delay line (also properly terminated). Output taps drive resistor summing array to achieve a wider pulse for a "slow" S/H with decent accuracy; its hold time is not relevant as the output can be cascaded to either a A/D or another, more robust S/H.
If you dislike the resistor array, the output delay line can be made nonlinear for pulse stretching at the output.
3,643,110 = 8 bits, 1uSec. Not too close to 4nSec or to even 20 bits... Altho, the ECL structure (properly tweaked) should easily allow the 4nSec. Still, 20+ bits seems rather iffy.
Wow! That's outside the box! Totally forgot about a 'mechanical' solution to this 'electronic' problem.
I like the idea of a 'passive' solution. The actual implementation seems daunting, but still. I forgot all about the delay line. Remember it being used to make some simple FM receivers. Will keep this in mind for use at
1GHz, where the physical dimensions make more sense.
It is very difficult to make a delay line that is longer than half a phase of the highest frequency for a required bandwidth. BTDT, a lot, didn't enjoy it. Phase, amplitude, group delay, all that begins to be increasingly messed up and you won't have a chance to come even close to your 20-22bit accuracy.
Now there are tricks to transfer a signal into another entity, for example into an acoustic wave (SAW) or an electromagnetic wave (coax) and create longer more accurate taps that way. But this becomes hugely complex if you require tons of taps.
IMHO your best bet is a time-staggered S&H and even then 20-22 bits at this kind of speed is a stretch. Maybe if you liquid-cool, calibrate and temp-control it to within 0.01 degree Kelvin :-)
-- Regards, Joerg http://www.analogconsultants.com/
Hey! Use a 555 timer in a super chilled Fluorinert bath!
Seems like the hard way to make a "simple" FM receiver. I can buy a channel-scanning FM receiver with headphones for about $4 at Walgreens.
-- John Larkin Highland Technology, Inc picosecond timing laser drivers and controllers jlarkin att highlandtechnology dott com http://www.highlandtechnology.com
Problem solved with physically realizable components! Actually got to
20-21 bits.Thanks VERY much to everyone who responded! Your circuit topology suggestions were awesome, but ALWAYS applicable are the "consider this" comments that keep any solution inside reality. We can 'bend' the laws of physics, but rarely break them.
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