Any OR gates with good noise immunity?

--
If the trigger is coming from the solenoids\' magnetic fields
collapsing, maybe a snubber across each of the solenoids, or a
little lowpass filter at the input of the 4071 just big enough to
kill the spike?

Your problem sounds an awfull lot like a variation of ground bounce issue that I experienced in a design. In our of our products, we were using a board that suffered from intermittant flase triggers when there was a disturbance in the mains power, such as when electromechanical devices would switch and would occur about 1 out of 10 times.

The problem in my case was due to a lack of a proper ground plane and adequate bypass capacitors. The board designer believed that putting one 10uF capacitor with a .1uF in parallel with it about 1 inch from a logic device with four power pins was adequate bypass. Similarly, he did not feel that it was necessary to put a bypass capacitor on any of the logic ICs. The problem was resolved with a redesign of the board that utilized a solid ground plane, on a two layer board, added proper bypass caps, and switched the design from through hole to surface mount which has a much lower lead inductance on the packages.

This brings me to the questions regarding your design. Are you using a ground plane and what do you have for bypass capacitors on the driver and receiver devices?

Another thing to consider is how long are the copper runs. You said that you are running from one board to another through edge connectors, which suggests that they may be of fairly decent length. It is likely that the design will require proper termination of the transmissions lines. Your runs will act as a transmission line, as opposed to a lumped circuit, if the run length is more than about 1/6th of the signal's propegation delay, which is a function of the PCB geometry and material. It is a common misconception that a "high speed" circuit means fast clock rate, when in fact it is a function of the signal rise times. This brings me to my final questions, what do you have for termination on the lines, how long are the copper runs, and what is the driver rise time (either from a datasheet or from measurement, though you will need to measure with something other than a capacitive scope probe). If you don't know these paramaters, I would guess that based on typical PCB construction if your lines are more than about 4 inches they will require termination.

I appologize if you are already familiar with the topics I descibed above, but I figured it would be less offensive to tell you something you already know that to leave something out that you needed to know.

Since you have a grounded metel enclosure, the best solution would be to determine how the noise is getting into the enclosure and a stopping it from getting in. You don't say if the solonoids are driven by circuits inside the enclosure in which case filtering or snubbing the drive circuits might help. A low pass filter at the input of the OR circuit might stop the external noise but could lead to false triggering of the shift register due to the slow rise time at the input of the OR causing multiple pulses as you go thru the threshold. Keeping noise out is always better than patching the internals.

--
Dan Hollands
1120 S Creek Dr
Webster NY 14580
585-872-2606
dan.hollands@gmail.com
www.QuickScoreRace.com

If you are not using a ground plane on the motherboard, you should provide a separate ground path for the logic circuit, so that none of the current through the noise-making relays can flow through the ground that supplies power to the logic.

If the signal(s) involved are not fast, series resistance can be added, possibly with shunt capacitance. This works wonders, and it reduces ESD damage susceptibility at the same time. However, start by reducing spike magnitudes at their source, if possible. Shunt diodes across solenoid and relay coils can help a lot. Paul Mathews

You could try an old trick-- put a R/C network right at the input pin.

100K and 1nF will damp any spikes roughly shorter than 10usec.

I know, not good digital design to add analog elements, but sometimes you just have to.

Thanks to all for your suggestions so far. The circuit is comprised of through-hole components on double-sided boards that are flooded with ground planes, except for the motherboard. I use 100nF bypass capacitors. The copper line in question is approximately 7 inches long in total, of which an inch is on the motherboard. The solenoids are not driven by or connected to my circuit. Switching speeds are very low, with the pulse being generated by a monostable (duration of almost 1s) through a diode, so that a separate circuit can latch the state (using a FET switch with feedback). A 22K resistor to ground enforces the low state of the line when a different pulse switches off the FET. Should this resistor be bypassed with a 100nF cap (thereby bypassing the OR gate input to ground), or would the suggested RC network at the OR gate input be better?

John.

Sounds like that whole area is already made up of MML (Mickey Mouse Logic). Sorry.

The *best* way would be to redesign it to be all digital clocked logic, but it's probably too late for that.

Take some small comfort, you're not the first engineer to have this problem.

Back around 1974 our department bought some $4000 Crown tape decks, with logic controlled push-buttons. The logic consisted of one small board with the old Fairchild 9xx RTL logic chips. In case that was before your time, RTL was a very early IC logic, like about the first available to anybody other than the military. It ran off +3 volts, and each input went directly to the base of a transistor, through an internal 400 ohm resistor. That made the noise immunity about 0.5 volts, maximum!

The tape decks turned out to be unusable. Just the action of the tape rubbing against the reels in rewind or fast-forward was enough to set off tiny static discharges, usually too small to hear or see, but enough to trip the logic from rewind to FF or Play! This happened about every 10 seconds! Days of my playing with extra bypass capacitors was to no avail.

In your situation I'd try the same thing, start with a large (100nF) capacitor, if that squelches the problem, try one ten times smaller, until it fails again, then go up to the next power of ten.

You don't want to use really large capacitors, as it's not a good idea to hold the gate in any state between 1 and 0 for very long. It could oscillate, or overheat, or fool the next stage.

You need to tell us more about this "FET switch with feedback" latching "the" state and what this has to do with the OR gate and CLKing the SR. After low power consumption, CMOS is mainly used for the largest possible noise immunity attainable by a logic family- making it unlikely that noise pickup is the real problem.

Who knows- capacitor bypass does no good when charged from a low impedance source. Why don't you sketch out this masterpiece and post it somewhere you can link us to.

The MOSFET is used to latch a transistor that drives a 30mA IR LED. Instead of taking a shortcut by tapping off this, I should have wired the monostable directly into the S input of an S/R latch IC and connected the Q output to the OR gate and the transistor that powers the LED. Lesson learned. In any case, a 10nF capacitor across the 22K resistor solved the problem. I've tested over 200 solenoid actuations since without trouble. Thanks.

That fix doesn't mean anything, it is strictly experimental and blind. You could be talking about anything and the logic should have achieved steady state long before the solenoid actuated if that's what it's doing. You could be talking about anything: View in a fixed-width font such as Courier.

. . . 5V . | . .-------+ . | | . | [R] . | | . | a . | k ~~ IR . -| | . p |-----+ . -| | . | | . | | ____ . | | \\ \\ . | | | >---> to sr clk . +-------|-------/___/ . | | . | | 4071 . [Rd] | . | | . | | . | | . | |/ . >----|>|-----+-----| . | |>

. [22k] | . | | . --- --- . . . . 5V . | . .-------+ . | | . | [R] . | | . | a . | k ~~ IR . >| | . |-[Rb]+ . /| | . | | . | | . | | ____ . | | \\ \\ . | | | >---> to sr clk . +-------|--------/___/ . | | . | | 4071 . | | . [Rc] | . | | . | |- . >----|>|-----+-----| n . | |- . [22k] | . | | . --- --- . . . . 5V . | . [R] . | . a . k ~~ IR . | . |- . .----------------------+---| n . | | |- . | | | . | ____ | --- . off >-------|--------------\\ \\ | . '----\\ \\ | o--+------> to sr clk . | o----/___/ . on >-------+----/___/ . | 4001 . [10k] . | . --- .

See...

for one way to handle big-time noise.

I had another version, somewhat simpler, but I haven't located it yet.

...Jim Thompson

--
|  James E.Thompson, P.E.                           |    mens     |
|  Analog Innovations, Inc.                         |     et      |
|  Analog/Mixed-Signal ASIC\'s and Discrete Systems  |    manus    |
|  Phoenix, Arizona            Voice:(480)460-2350  |             |
|  E-mail Address at Website     Fax:(480)460-2142  |  Brass Rat  |
|       http://www.analog-innovations.com           |    1962     |
             
     It\'s what you learn, after you know it all, that counts.

we used to use a 12V variant of TTL circuits back in the 80's in flash LASER systems so as to not be upset by the firing of the flash bank.

"Jim Thomps>

[snip]

In systems where I know where the noise is going to occur (such as a car ignition system) you just blank during that interval. In my CD ignition designs the distributor pickup was blanked while firing was occurring.

...Jim Thompson

-- | James E.Thompson, P.E. | mens | | Analog Innovations, Inc. | et | | Analog/Mixed-Signal ASIC's and Discrete Systems | manus | | Phoenix, Arizona Voice:(480)460-2350 | | | E-mail Address at Website Fax:(480)460-2142 | Brass Rat | |

| 1962 | It's what you learn, after you know it all, that counts.

Thanks for taking the time to do the schematics Fred. The relevant portion of my cct is below along with the new cap. . ------------ P . | | . | +--- . |/ | .Set>---|>|--+--[R]----| | . | |> | . | | | . | | | . | --- | . | | ____ . -----------------------+-----+---Long track--\\ \\ . | | | >--->

. | | /___/ . New cap --- [R] . --- | . | | . -----+ . | . --- Best viewed in fixed font again

Thanks to Fred for taking the time to draw those schematics. The relevant portion of my cct is below along with the new cap. . ------------ P . | | . | +--- . |/ | .Set>---|>|--+--[R]----| | . | |> | . | | | . | | | . | --- | . | | ____ . -----------------------+-----+---Long track--\\ \\ . | | | >--->

. | | /___/ . New cap --- [R] . --- | . | | . -----+ . | . --- Best viewed in fixed font again.

My circuit does not actuate solenoids, but it's installed in a machine with plenty of them. The noise blanking suggested by others is very interesting, but since solenoids can be actuated at any time, I don't know if this approach would work in my case.

Thanks to Fred for taking the time to draw those schematics. The relevant portion of my cct is below along with the new cap. . ------------ P . | | . | +--- . |/ | .Set>---|>|--+--[R]----| | . | |> | . | | | . | | | . | --- | . | | ____ . -----------------------+-----+---Long track--\\ \\ . | | | >--->

. | | /___/ . New cap --- [R] . --- | . | | . -----+ . | . --- Best viewed in fixed-width font again.

My circuit does not actuate solenoids, but it's installed in a machine with plenty of them. The noise blanking suggested by others is very interesting, but since solenoids can be actuated at any time, I don't know if this approach would work in my case.

In the future use the logic to do the latching. You have no noise immunity to speak of on the NPN base, anything more than 0.5V or so and it's triggered. I suspect the problem is a power supply transient coupling through the P-channel Csd into the high impedance below.

That makes sense. I'll stick with logic latches next time. Thanks.