The question about the pros and cons of different mixers might soon be in the past, since direct sampling ADCs perform surprisingly well.
One WebSDR receiver
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samples the
0-30 MHz band and then digitally decimates the requested sub-band for individual listeners across the Internet. Unfortunately, the antenna is in the middle of a noisy campus area, thus it is hard to say something about the actual weak signal performance. However, I didn't detect any obvious spurious responses as with some ordinal receivers.
For single frequency reception at one time, much slower sampling rates (fs) and hence cheaper or more accurate ADCs can be used by limiting the analog front end bandwidth well below fs/s then undersampling, thus no need for a mixer in front of the ADC.
Hey I'm a semi-retired shrimp seller with a little bit of technical skill. I did a good job of replicating the circuit, I didn't design it. I can only explain operation on a simple level. If I had more knowledge I would have corrected the distortion at increased input levels. I suspect a good analog engineer would have done a lot of things different to reach the goal of high input impedance, 50 ohm output. On the other hand Kleijer built a working circuit and later went back and built an improved second version. I follow the crystal radio community and have not heard of anyone else that built the circuit, it's a shame because it is a very useful piece of equipment for experimenting with high Q LC circuits. I hope to take dagmar's design and improve it further.
?? I have looked for a data sheet on the BF256C, all I can find is very limited info, Anyone find a data sheet with the device capacitances? Mikek
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Maybe. Seems like a lot of foofaraw just for a sportscast. ;)
SDR-style spectrum analyzers are pretty much entry-level junk compared with the traditional approach. Lots of bells and whistles, lots faster measurements, but in my world if you can't measure something, not-measuring it fast is no better than not-measuring it slowly.
Cheers
Phil "Big boat anchor fan" Hobbs
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The enclosure should be grounded! Let's not confuse that with bootstrapping the input coax's shield (which you'll only do _if_ you use coax).
So yes, the enclosure should be isolated from the driven shield that is shown in the schematic.
(My shield-driver is pretty wimpy, only suitable for a very short, low- capacitance run. Might need beefing up.)
If you build it, it'll be fun to hear what output voltage you get from this stage when you drive your 0.3pF input cap with, say, 50mV AC. If you put 50mV into the 0.3pF and get 25mV out the back end, that means our net input capacitance after bootstrapping is about the same as your series 0.3pF.
He's bootstrapping the input impedance to avoid loading the FET stage. Kleijer's crafty.
ISTM Kleijer did a very decent job, and got something more than good enough for his task. And was nice enough to share it with everyone.
+1 for Kleijer.
We could do that, but it would add complexity without much benefit to your application. Using an op-amp buffer instead of a BJT follower is one possibility...
There's nothing stopping us from running the JFET at Vgs=0. That just runs it richer.
In the old days, all the various JFETs were selections taken from one of several different processes. Fairchild's BF256B datasheet says it's made on Process 50, so it should have pretty much the same capacitances as any other JFET from the same process, e.g.,
OK, so I ground the enclosure to (battery) ground and use an isolated input connector. I have some isolated BNC connectors that will work great.
My plan is to build this into a setup that has my highest Q tuning cap and sitting just below the cap. So a short run. Hope to rectify* and drive a voltmeter with some type of attenuator.
*Maybe even a peak detector.
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If the design is sensitive to external noise, it might be useful to use triaxial cable with the inner shield driven as a guard and the outer shield grounded to the case.
With the input impedance this circuit has I don't see how it wouldn't be sensitive to noise. But with such a short run of wire I suppose noise is not much of an issue.
Oh I'm not offended, trust me. I was agreeing with you that my circuit's performance could be improved on. I'm well aware, we just don't need it. Give me one more transistor and it could be markedly better still, but we don't need it. It's a waste to overcomplicate a thing.
I was also giving thumbs-up to Kleijer. A schematic is a window into the designer's soul. Kleijer has soul.
they are offset up or down in a strip* so that as they pass two pickup coils they trigger pulse on terminal "0" or terminal "1" , fairly rare these days, but the electrical interface is still supported by modern RFID readers.
(*) so techically array is correct: an array with two rows, each row being the boolean inverse of the other
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OK, The circuit is built, I haven't tested it. I'm testing just the circuit just the circuit posted. I want to know how to drive the input. Say I connect a 9 inch piece of RG58, that's 19pf, is that to much? I want to drive it with a 50 ohm sig/gen. Can I terminate the RG58 with 50 ohms or do I need to feed the RG58 with a high impedance? Maybe a series 1Mohm. I don't see how to separate the sig/gen cable from the input cable. May I just need to connect it to the LC and see what I get. Thank, Mikek
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Easier said than done. I have a pretty good capacitance tester. I made a .3pf cap :-/ and used an 82pf cap plus the probe, together they measured 106.7pf. I applied 16Vpp and measured 0.06Vpp at A. 16 / 0.06 = 266.6 The voltage ratio is 266.6.
106.7 / 266.6 = 0.4 That makes my cap look like 0.4pf
I measured the capacitance of a 6" x 8" piece (48sq in) of the PCB I make my caps from, it measured 990 pf. 990 / 48 = 20.63pf per sq in. My cap is 1/8" diameter or 0.01227 sq in. So, 1sq in / 0.01227 sq in = 81.53
20.62pf/sq in / 81.53 = 0.253pf per 1/8" dia. So fringing and lead to lead capacitance, I'm in the ballpark, just not sure what field. If you have any suggestions, I'm willing. Way past my bedtime, good night. Mikek
PS. PCB is Rogers Duroid 5880, I could not find a capacitance per sq in number online.
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Don't they give a dielectric constant? That is important in RF work as it impacts signal speed, impedance, etc. From that you can calculate the capacitance (ignoring fringe effects). I'm not familiar with calculating fringe effects, but it's hard to imagine there wouldn't be a simple way to figure that out for a pair of round disks separated by a dielectric. But I don't know for sure, even this might best be done with a 3D field solver. lol
I think the parasitic capacitance of the other parts of the circuit would be in this same ballpark, so I don't know how you would be able to get close to the true value other than by measuring.
I will say I am impressed with what you have done so far. As Edison said, "invention is 1% inspiration and 99% perspiration".
Yes the dielectric constant is 2.20. I don't know how to figure the capacitance from that, so it was easier to measure it than search out how to calculate it.
separated by a dielectric. But I don't know for sure, even this might best be done
Over my pay grade.
I thought of a different way physically to connect this up for measurement, basically just tightening up the circuit. It should eliminate the 60 Hz I had on the measurement, and maybe eliminate some parasitic capacitance.
Let's not get carried away, all I did was build someone else's circuit. Now that I'm mostly retired, I get a chance to do these things. The real stumbling block is getting off the computer and doing them. By the time I check my email, read the usenet groups check stock futures, check my homepage, read a financial guru's page, check a crystal radio forum and read another financial forum, 4 hours are gone from my day. OK, going to the bench now. Well, after I check the market futures! Mikek
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I got out my better probe (Tek 6122 11pf) and made curly cues for the probe tip. Here's a picture of the tightened up circuit.
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The new total capacitance, probe plus 82pf cap is 94pf. (measured)
16Vpp input, V(A) is 0.068Vpp. Then 16/0.068 = 235.3
235.3 / 94 = 2.5pf. This is a tighter measurement and also agrees with my calculation of
0.253 that I calculated for the pcb capacitance per sq in. Rather than fight with a new piece of pcb material just slightly over
1/8" in diameter. I'm going to go with a new value input cap of 0.25pf. If you see this as a bad idea, let me know and I'll fumble around and make a larger cap. I used a 1/8' paper punch to make this cap, I could use a 1/4" and grind it down, but it's a chore.
Now for the next measurement. Is this with a T1 in the completed circuit? Or, do I add the probe + 82pf back in to get a ratio? Ya, I'm now confused. I think we might want the voltage at the gate, but I think that would be an impossible measurement. ie putting 11pf probe across a 0.3pf cap ? Thanks, Mikek
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You're close enough for our purposes. The first measurement may be being affected by stray capacitances, dunno. In the end all we'll care about (when you use this thing) is getting 100mV out for 100mV in.
n
No, that should be 94pF * (.068V / 16V) = 0.4 pF.
It looks to me like your input cap is good, and 0.4pF. No need to change it.
Yes, it's time to use your calibrated in the completed, working circuit. We'll want to measure the a.c. signal at the FET source first, then the FET's drain.
Sorry, I wasn't clear enough. We're measuring in-circuit.
To check the effective input capacitance we want to know the attenuation of the input a.c. voltage, as measured at point (A).
Rationale: The input voltage will be divided across your 0.40pF input capacitor and the circuit's input capacitance:
We can't measure at the gate--that's too high impedance--so we're measuring at FET T1's source terminal, point (A).
If 63% of the voltage is lost across the 0.40pF series cap, then the effective input capacitance is dropping 37%, which means the series cap is 63% of the total reactance and Ceff is 37% of the total reactance.
You can measure Vac at the FET source on the original circuit for compariso n, too. That's a good way to assess the relative performance of the new circu it vs. the original (after correcting for any differences in the input couplin g caps, of course.)
(Kleijer said his input division ratio was 17:1, indicating his circuit's input capacitance (Ceff) was 16 units, and his coupling cap was 1 unit of capacitance, or Ceff = 16 x Ccoupling.)
We want to know the a.c. voltage @ (B) just to gauge how well our drain portion of the bootstrap is working. The closer Vac(B) is to Vac(A), the better we're doing. 1:1 would be ideal. 0.9 would be okay, less than 0.9 indicates a problem.
Here's the circuit, for reference, with probe points (A) and (B) marked:
(Remember, I'm showing a boot-strapped coax on the input, but we're not using that yet. We want to keep the comparisons apples-to-apples, and change only one thing at a time.)
C is capacitance in Farads, Eo is permittivity of free space, Eo = 8.854x10-12 F/m, k is relative permittivity a.k.a. dielectric constant of medium = 2.2, A is area of plates in meters, d is distance between plates in meters
Bob's your uncle.
Also over your budget. But someone who uses one at work could solve it for you. But like I said, for two round plates, this should have been reduced to a formula somewhere. The smaller the plates and the closer together, the larger the fringe effects will be (I think, maybe smaller plates and farther apart mean larger fringe effect).
Tightening up the circuit? Are you using wrenches or a screwdriver? You mean make it smaller?
The only part of the circuit that matters is the input resistors and the gate of T1. I'm pretty sure the rest of the circuit will only have much smaller secondary effects on the input capacitance. All that should be mitigated by the low value of the series cap. But the leads coming to the cap have capacitance too, just less. But this cap is so small even the capacitance of the leads can be significant. That's the tradeoff, make the cap smaller and the parasitics are larger in comparison. Make the cap larger and it is less of a divider presenting a larger capacitance to your circuit.
I think you are following in Kleijer's footsteps and doing a great job. That's my point. You are doing the perspiration part to extend Kleijer's amp design.
I read your other two posts. I think you did a good job with the cap, but I'm not sure you can measure the T1 gate capacitance that way. Won't the value vary with the bias point? As the gate voltage varies the width of the depletion zone varies and so the capacitance. So I think you should calculate that capacitance, or maybe not worry about it since it is going to be reduced greatly by the bootstrapping circuit. Actually, the data sheet I have for the BF256C includes a graph of input capacitance vs. gate-source voltage. Can't you read it from there?
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