annular rings in vias

My guess is that it would be OK if the vias are laser-drilled. Otherwise I'd be a bit concerned about material damage letting plating solution into the weave and maybe causing shorts.

Haven't got any data either way, though.

Cheers

Phil Hobbs

I'm pretty sure that it is a common optimisation for PCB manufacturers in any case.

I looked into it when I was trying to fit more traces on inner layers between vias. I believe it is fine (and likely normal) to omit the "unused" inner layer annular rings but it did not help me because the annular ring requirement was mainly for drill tolerance. So you can't get a track any closer to the hole than was already set by the "min AR + gap" requirement in any case.

There might be other reasons to omit them of course, capacitance or something.

You mean, PADS doesn't automatically remove unconnected inner rings?

Tim

-- Seven Transistor Labs, LLC Electrical Engineering Consultation and Contract Design Website:

Den onsdag den 11. oktober 2017 kl. 19.31.10 UTC+2 skrev John Larkin:

it is called removing "non-functional pads" on inner layers

afaiu some manufacturers do it by default because it saves on drills and apparently makes for a more reliable via

Some tools can do it automatically, but if you need the added space for routing I think you need a bit more trickery

John Larkin wrote on 10/11/2017 1:30 PM:

It sounds like you are trying to work around a limitation in your layout software. Are you saying your CAD package won't remove the annular rings on inner layers when there is no trace connecting to the through hole? So to work around this you want to turn off *all* inner layer annular rings and let the traces provide the annular ring connection by being large enough.

Why not use the CAD tool correctly or get a proper CAD package?

Yes, it is so that I can push wide traces between a row of connector pins. Zero annular rings give me maximum clearance for fat traces on some layers. But I'll need to connect fat traces to various connector pins on other layers.

I'm pushing fusing current limits on the traces, so I don't want to neck them down to sneak between the blocking pins.

Den onsdag den 11. oktober 2017 kl. 20.45.21 UTC+2 skrev rickman:

I suspect John just haven't found the button that says "remove unused pads" or something to that effect

Yes, all the PCB packages I've used do that by default. If there is no trace or plane coonecting to that via, then there is no pad drawn there. if there is a plane or pour on that layer, then there will be a big hole punched in the plane to avoid the drill hole.

It may take some default setting in the pad stack or whatever to make your package do this.

Jon

OK, this can be dangerous. The mechanical drill cuts glass fibers, and can deform them and the surrounding epoxy. This can allow the barrel plating to enter the space around the drilled hole. So, don't get conductors too close to the hole wall or you could get shorts. it is also possible to have boards that pass electrical test and then short out during soldering processes or later.

You might ask your PCB fabricator how close to the hole wall is safe.

Jon

I don't think he is trying to ignore the barrel/hole to trace spacing. He is just trying to get rid of the annular ring. I don't know why this is such a big deal to do. Every CAD package I have used allows this.

How about necking down and doing two layers in parallel?

Cheers

Phil "bigger hammer" Hobbs

I have used a CAD package that shows the pads in layout even if they are removed before generating the Gerber files. Maybe he is looking at the layout screen rather than the Gerber files or just reading the f***ing manual.

I may do two or three layers in parallel already!

At some point my current could blow up the connector, but connectors can be replaced.

It sounds like I can specify my connector and power-via pad stacks without internal annular rings. Then I can use maximal traces widths between unconnected pins without throwing design-rule checks. Removing the unused rings at Gerber time isn't the same thing.

Assuming they don't catch fire. ;)

Cheers

Phil Hobbs

Am 11.10.2017 um 22:03 schrieb rickman:

If the Gerber files are different from what I see on the screen, the production file generation is broken.

Den onsdag den 11. oktober 2017 kl. 22.22.55 UTC+2 skrev John Larkin:

found this, seems like it should work with DRC and all

Gerhard Hoffmann wrote on 10/11/2017 4:40 PM:

If you say so. The screen is a representation which allows you to manipulate the layout. It is not directly editing the Gerber files. In one package I have used in the past it used a variety of methods to convey what is happening with the layout as you edit it. Visualizing every detail of the pad stack was not one of those things that matched the Gerber file perfectly. I seem to recall the drill hole was represented by a small X. Is that also an error?

We don't use the PADS split/mixed plane feature. It's more trouble than it's worth. All our planes are conventional routing layers, and we just draw copper (or traces!) where we want.