I've now got a simulation of the variable voltage version of the Baxandall photomultipler power supply.
C1 has been pushed up to 3.3nF, equivalent to about half the 10pF inter-win ding capacitance of the output secondary L3. The leakage inductance of the transformer, even with a coupling factor of 99%, puts a bit of high frequen cy ripple on the output waveforms [V(ct),V(tank+)and V(tank-)]. Making C1 a n appreciable fraction of the reflected secondary capacitance lowers the op erating frequency appreciably - the circuit is set to run at 43.5kHz, when the original target was 100kHz - but it does tame the ripple.
Version 4 SHEET 1 2176 1652 WIRE -576 -208 -608 -208 WIRE -384 -208 -512 -208 WIRE -80 -208 -384 -208 WIRE 320 -208 -80 -208 WIRE 320 -160 320 -208 WIRE -384 -144 -384 -208 WIRE 1552 -80 1552 -112 WIRE 1728 -80 1680 -80 WIRE 1824 -80 1792 -80 WIRE 1904 -80 1824 -80 WIRE 2080 -80 1968 -80 WIRE 320 -32 320 -96 WIRE -128 -16 -288 -16 WIRE 112 -16 -48 -16 WIRE 272 -16 112 -16 WIRE 1680 32 1680 -80 WIRE 1824 32 1824 -80 WIRE 992 144 944 144 WIRE 1088 144 992 144 WIRE 1216 144 1168 144 WIRE 1264 144 1216 144 WIRE 1424 144 1344 144 WIRE 1472 144 1424 144 WIRE 1680 176 1680 96 WIRE 1824 176 1824 96 WIRE 1936 176 1824 176 WIRE 2080 176 2080 -80 WIRE 2080 176 2000 176 WIRE 320 224 320 64 WIRE 640 224 320 224 WIRE 752 224 704 224 WIRE 1120 224 832 224 WIRE 1216 224 1216 144 WIRE 1216 224 1120 224 WIRE 2080 224 2080 176 WIRE 944 304 944 144 WIRE 1152 304 944 304 WIRE 1472 304 1472 144 WIRE 1472 304 1216 304 WIRE 2080 352 2080 304 WIRE -608 368 -608 -208 WIRE 944 464 944 304 WIRE 320 528 320 224 WIRE 2000 528 1904 528 WIRE 2080 528 2080 432 WIRE 2080 528 2000 528 WIRE 576 544 496 544 WIRE 752 544 656 544 WIRE 896 544 752 544 WIRE 1472 544 1472 304 WIRE -32 608 -160 608 WIRE 176 608 48 608 WIRE 272 608 176 608 WIRE 1056 624 768 624 WIRE 1248 624 1136 624 WIRE 1424 624 1248 624 WIRE -160 656 -160 608 WIRE 2080 656 2080 528 WIRE -288 672 -288 -16 WIRE 496 672 496 544 WIRE 768 672 768 624 WIRE 1904 672 1904 528 WIRE -608 816 -608 448 WIRE -384 816 -384 -80 WIRE -384 816 -608 816 WIRE -288 816 -288 752 WIRE -288 816 -384 816 WIRE -160 816 -160 736 WIRE -160 816 -288 816 WIRE 320 816 320 624 WIRE 320 816 -160 816 WIRE 496 816 496 752 WIRE 496 816 320 816 WIRE 768 816 768 752 WIRE 768 816 496 816 WIRE 944 816 944 560 WIRE 944 816 768 816 WIRE 1472 816 1472 640 WIRE 1472 816 944 816 WIRE 1680 816 1680 256 WIRE 1680 816 1472 816 WIRE 1824 816 1824 176 WIRE 1824 816 1680 816 WIRE 1904 816 1904 736 WIRE 1904 816 1824 816 WIRE 2080 816 2080 736 WIRE 2080 816 1904 816 WIRE -608 864 -608 816 FLAG -608 864 0 FLAG 992 144 tank- FLAG 1424 144 tank+ FLAG 1120 224 ct FLAG 1248 624 M1-drive FLAG 752 544 M2-drive FLAG 176 608 N-FET-M3_drive FLAG 112 -16 P-FET_drive FLAG 2000 528 Out FLAG -80 -208 +12V SYMBOL ind2 1072 160 R270 WINDOW 0 32 56 VTop 2 WINDOW 3 4 56 VBottom 2 SYMATTR InstName L1 SYMATTR Value 0.220m SYMATTR Type ind SYMATTR SpiceLine Rser=0.022 Cpar=38p SYMBOL ind2 1248 160 R270 WINDOW 0 32 56 VTop 2 WINDOW 3 4 56 VBottom 2 SYMATTR InstName L2 SYMATTR Value 0.220m SYMATTR Type ind SYMATTR SpiceLine Rser=0.022 Cpar=38p SYMBOL nmos 1424 544 R0 WINDOW 0 -49 26 Left 2 WINDOW 3 -80 114 Left 2 SYMATTR InstName M1 SYMATTR Value AP9465GEM SYMBOL nmos 896 464 R0 SYMATTR InstName M2 SYMATTR Value AP9465GEM SYMBOL voltage -608 352 R0 WINDOW 123 0 0 Left 2 WINDOW 39 24 132 Left 2 SYMATTR SpiceLine Rser=1 SYMATTR InstName V1 SYMATTR Value 12 SYMBOL pmos 272 64 M180 SYMATTR InstName M4 SYMATTR Value FDS4435A SYMBOL voltage 496 656 R0 WINDOW 3 -4 202 Left 2 WINDOW 123 0 0 Left 2 WINDOW 39 0 0 Left 2 SYMATTR Value PULSE(0 9 11.5u 0.02u 0.02u 11.35u 23u 5000) SYMATTR InstName V2 SYMBOL voltage 768 656 R0 WINDOW 3 -8 234 Left 2 WINDOW 123 0 0 Left 2 WINDOW 39 0 0 Left 2 SYMATTR Value PULSE(0 9 0u 0.02u 0.02u 11.35u 23u 5000) SYMATTR InstName V3 SYMBOL voltage -288 656 R0 WINDOW 3 -37 200 Left 2 WINDOW 123 0 0 Left 2 WINDOW 39 0 0 Left 2 SYMATTR Value PULSE(12 0 2.25u 0.02u 0.0.2u 6.9u 11.5u 10000) SYMATTR InstName V5 SYMBOL res -32 -32 R90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName R4 SYMATTR Value 47 SYMBOL ind2 1696 272 R180 WINDOW 0 36 80 Left 2 WINDOW 3 36 40 Left 2 SYMATTR InstName L3 SYMATTR Value 642m SYMATTR Type ind SYMATTR SpiceLine Rser=64.5 Cpar=10p SYMBOL res 2064 640 R0 SYMATTR InstName R6 SYMATTR Value 3300k SYMBOL res 2064 208 R0 SYMATTR InstName R7 SYMATTR Value 2.2k SYMBOL cap 1888 672 R0 SYMATTR InstName C2 SYMATTR Value 10n SYMATTR SpiceLine V=3k SYMBOL ind 2064 336 R0 SYMATTR InstName L13 SYMATTR Value 47m SYMATTR SpiceLine Rser=52 Cpar=37.5p SYMBOL cap 1792 -96 R90 WINDOW 0 0 32 VBottom 2 WINDOW 3 32 32 VTop 2 SYMATTR InstName C3 SYMATTR Value 10n SYMBOL diode 1968 -96 R90 WINDOW 0 0 32 VBottom 2 WINDOW 3 32 32 VTop 2 SYMATTR InstName D1 SYMBOL cap 1936 192 R270 WINDOW 0 32 32 VTop 2 WINDOW 3 0 32 VBottom 2 SYMATTR InstName C4 SYMATTR Value 10n SYMBOL diode 1808 32 R0 SYMATTR InstName D2 SYMBOL cap 1216 288 R90 WINDOW 0 0 32 VBottom 2 WINDOW 3 32 32 VTop 2 SYMATTR InstName C1 SYMATTR Value 3.3n SYMBOL res 1152 608 R90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName R1 SYMATTR Value 47 SYMBOL res 672 528 R90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName R2 SYMATTR Value 47 SYMBOL ind 848 208 R90 WINDOW 0 5 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName L4 SYMATTR Value 1m SYMATTR SpiceLine Rser=1.8 Cpar=63p SYMBOL FerriteBead 672 224 R270 WINDOW 0 16 0 VTop 2 SYMATTR InstName L5
SYMATTR SpiceLine Ipk=1 Rser=0.3 Rpar=587 Cpar=1.216p mfg="Wurth Elektronik eiSos" pn="742 792 18" SYMBOL FerriteBead 1680 64 R0 SYMATTR InstName L6
SYMATTR SpiceLine Ipk=1 Rser=0.3 Rpar=587 Cpar=1.216p mfg="Wurth Elektronik eiSos" pn="742 792 18" SYMBOL FerriteBead -544 -208 R270 WINDOW 0 16 0 VTop 2 SYMATTR InstName L7
SYMATTR SpiceLine Ipk=1 Rser=0.3 Rpar=587 Cpar=1.216p mfg="Wurth Elektronik eiSos" pn="742 792 18" SYMBOL cap -400 -144 R0 SYMATTR InstName C5 SYMATTR Value 100n SYMBOL nmos 272 528 R0 SYMATTR InstName M3 SYMATTR Value FDS6680A SYMBOL res 64 592 R90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName R3 SYMATTR Value 47 SYMBOL voltage -160 640 R0 WINDOW 123 0 0 Left 2 WINDOW 39 0 0 Left 2 WINDOW 3 -170 247 Left 2 SYMATTR Value PULSE(0 5 9.73u 0.02u 0.02u 3.8u 11.5u 10000) SYMATTR InstName V4 SYMBOL FerriteBead 320 -128 R0 SYMATTR InstName L8
SYMATTR SpiceLine Ipk=1 Rser=0.3 Rpar=587 Cpar=1.216p mfg="Wurth Elektronik eiSos" pn="742 792 18" TEXT -328 992 Left 2 !.tran 0 100m 0 10n TEXT -336 928 Left 2 !.ic I(L4)=0.08 I(L3)=-0.00003 I(l6)=0.0 I(L1) =0 I(L2)=0.08\n.ic V(tank-)=3 V(ct)=1.5 V(tank+)=0 V(Out)=-1140 TEXT -328 1040 Left 2 !K1 L1 L2 L3 0.99
The idea is that a real circuit would be run with MOS-FET drive timings gen erated by a programmable logic device clocked by a VCO - probably the VCO i n a 74HCT4046 - whose operating frequency would be continuously (and automa tically) trimmed to match the actual resonant frequency of the device).
The 74HCT4046 has a guaranteed minimum operating frequency of 11MHz with th e control voltage at Vcc/2, so I'd design for a nominally 6.7MHz clock, giv ing me the 150nsec break-before make intervals I've put into the simulation as single clock periods. In reality, I might be able to get closer to 11MH z, and some programmable logic devices offer rather faster built-in VCOs.
My 23usec period is then 154 clock cycles, and the pulse width modulation o n the input to L4 can vary from 0/77 to 77/77, though the need to put in br eak-before make gaps makes the last step a big one - from 75/77 to 77/77.
Output voltage control is fairly coarse - 75 25V steps up to about 1850V an d a 50V step up to 1900V. One could feed an analog voltage into a monostabl e - running from say 50nsec to 200nsec - to add a finer control if it was desired, or one could just find (or make) a faster VCO and clock the system faster
The idea would be to have the "high" period of the PWM driving waveform lin ed up the middle of the peak voltage at the centre tap (V(ct) on the simula tion).
With the load simulated, the voltage at the centre tap rises rapidly for th e first 2sec of the cycle, flattens off for the next 5usec, starts falling
7usec after the start of cycle, gets halfway back down to 0V at 9usec and h its 0V at 11usec (give or take a bit of ripple).My thought would be that if the desired voltage is n/77 of 1900V, the initi al 0V period would be some (77-n)/4 clock periods long. In the simulation, n=60, and if I'd done that the P-channel FET would turn on about 0.6usec into the cycle.
In fact it turns on a lot later at 2.25usec, which reflects a quite a bit o f mindless tinkering. I can't be bothered to adjust it back to a more sensi ble place - it's not going to make much difference
If the clock were slower than 6.7MHz, the V(ct) voltage would still hit 0V after 11usec and stick at about -0.4V until the start of the next cycle.
The timing control loop would probably look at the trailing edge of V(ct)at two points - at around 60 clock edges into the cycle and around 72 clock i nto the cycle - and adjust the VCO frequency so that V(ct) would hit zero a t 77 clock edges.
There's no point in getting too excited about the fine detail until I get around to building a real circuit - the simulated ripple is likely to be wo rse than the real ripple, because both skin effect and the finite conductiv ity of the ferrite core are likely to kill the ripple quite a lot faster th an it dies away in the simulation. And there's very little chance that I'll ever build a real version of the circuit, unless a potential customer emer ges from the wood-work.