Hey gang, there are maybe better places to ask, but googling reveals very little on this topic. we are using a maxii cpld. I am not directly involved in the design of this part of the circuit, so i don't have much knowledge of the cpld world. but... the datasheet says max prog/erase cycles is 100.
on page 61 of the datasheet
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what does the 100 cycles refer to? How are CPLDs programmed these days? What is in there exactly? RAM loaded by a flash on power up?
(I stopped design back when a 22V10 was a current part...)
Cycle is refered to a (one) program-erase cycle. (that is: you first program the chip with something, i.e. current design, then if you don't like it or you found a bug then you reuse the chip by erasing the chip and then you reprogram the chip again with the new content, and that is called a cycle). "100" is # of times you can erase/program chip before it fails to be reprogramed again, after that is being considered "burned" (broken, kaput, dead ...).
With programmers (devices) generally refered to as "download cables"
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In there is a programmable field (actually quite similar to 22V10's interconnect field) containing "fuses" being "blown" during programming. That 'field' interconnects logical gates and flip-flops. They are not being blown, it's just a figurative speach/expression. These 'fuses' are made of MOSFET transitors with insulated pocket of metal intrenched above "Gate" of the MOSFET, forming a tiny capacitor. After programming that 'pocket' holds the charge causing tranisitor to be closed. Discharging the pocket ("erasing") causes transistor to be open.
On Mar 25, 4:18=A0pm, snipped-for-privacy@netzero.com wrote: microsys.com
Some bits might retain data through erasure. Basically, some charge storage in the FLASH cells could occur that doesn't get erased fully, leading to bad bits or low gain (slow response on READ).
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