Advise for intel about integrating RAM onto chip.

snipped-for-privacy@hotmail.com wrote in news:d27e3361-d297-4bbe-ade9- snipped-for-privacy@googlegroups.com:

SNIP!

You are such an idiot.

I am pretty certain that Intel knows a lot more about things than you ever will, child.

Please don't, or we'll have to killfile you.

Just stacking RAM and CPU on separate chips in the horizontal direction or vertical direction is very boring.

I am interested if someone integrates a one gigabit of RAM with a SIMD (vector processor). A 32Krows x 32 Kcolumn RAM with 1024 parallel 32 bit ALUs would be an interesting parallel architecture.

snipped-for-privacy@downunder.com wrote in news: snipped-for-privacy@4ax.com:

IBM's 7nm stuff looks really cool. How they gonna connect up to that onto the outside world?

Whether stuffed gets stacked or not is a no-brainer. As things get smaller and less hot, we WILL start bringing other elements into closer proximity. So sure, we will see local arrays being used.

But dang, how they gonna hook all that shtuff up!

But the title of the post is integrating it onto the CPU chip. And of course Intel CPUs have had cache RAM since the 386. So, again, IDK what he's talking about.

Gigabit?

with a SIMD

• What are you talking about boy? Never heard of L1,L2 cache? That is RAM, kid.

Now THAT is more like it!

It should be noted how a dynamic RAM works.

On a 1 Gbit RAM the 15 bit row address selects one of the 32 K columns. The contents of all 32 K cells in that row are read out and forwarded into 32 K sense amplifiers and all the nits in that column are written back to 32 K cells in parallel.

On a read cycle the output of only 1-8 sense amplifiers are selected by the column address and forwarded to 1-8 I/O pins. On a write cycle. most of the column bits are written back as in a read cycle _except_ for 1-8 bits, in which the sense amplifier output is replaced by the I/O pin values. The column address defines, which bits of the column are taken from the I/O pins.

On a typical DRAM chip, the severe bottle neck is the memory _interface_ to the external world being only 1-8 bits wide, while internally 32 K bits would be available. It would be impractical to have 32 K external I/O pins :-)

If the ALUs are integrated on the same chip, all 32 K column bits could be accessed in parallel. Architecturally this would be simple to make a vector processor (SIMD) with say 1024 ALUs connected to the sense amplifier outputs A 32 bit column could support 2048 of 16 bit ALUs, 1024 of 32 bit ALUs or 512 of 64 bit ALUs (e.g. double precision floats each).

Skybuck's been the same age for the last twenty years.

RL

The Russkis tried something like that long ago, but I can't find the pic anywhere :/

NT

For a couple of years now, I have been trying to figure out exactly what is wrong with Skybuck.

So far, the top-3 contenders are:

1) He's off his meds (again) 2) A TV fell on his head as a child (I'm thinking a Kloss Nova Beam Model-1, three-lens projection TV, from an appreciable height!), or 3) He hasn't had sex yet; potentially even including himself. (Or if he has, it just wasn't as enjoyable as posting his drivel here.)

Or, maybe he's just crazy.

legg wrote in news: snipped-for-privacy@4ax.com:

He has spent way too much of the last five of it making inane posts into this group.

Did you see how cool that IBM 7 nm die looked? Wow. 30Bn elements on less space using way less power running faster. You could put 4 of them into a cellphone and have a quad quad. Or the cellphone PCB will be 900 sq mm and the rest will be a battery that makes it run for a month.

I hope they (IBM) come out with a new, super powerful, already scalar Power PC version of the CELL CPU. Then folks WILL be building supercomputers under their desks. Redux the CELL. That lil bastard would run circle around everything had they not clamped the clocks on it. Bring it back... Badder then ever. Emulate all that x86 and other intel multi-pipe crap easily and faster. Just add a primo graphics engine and set it up for AI too. Winner winner chicken dinner.

snipped-for-privacy@gmail.com wrote in news: snipped-for-privacy@googlegroups.com:

Ever seen our hand wired core rope memory?

Impractical? Yeah... path lengths alone.

Even today's architectures on the MOBOs make for timing issues and some traces have to have wiggles in them to slow down the arrival of their pulses with respect to their neighbors.

Kind of like how engine headers need equal length pipes to be in tune.

The F-35 stimulator racks I fitted with a few thousand high freq SMA cables all had to be equal length. You would not believe how cheap they get when you contract cable houses and look for bids on builds that big. And we did more than a few stimulators for the DoD. That is systems of 15 racks of a gazillion dollars worth of High Ghz gear). When they bought our gear, most of the bid goes into the gear. No cheating the gov boys when you are at 10 to 30GHz.

Instead of a few bucks a foot, they become a few bucks each (the cables). No way we could have matched that in house. Would have cost us millions, even if we produced higher quality product.

Did everyone see that TSMC is now leading Intel in process technology? They are shipping a lot of product on 7nm, including AMD cpus for all markets, while Intel only has it's mobile products on 10nm. TSMC will be rolling out 5nm later this year.

IDK what all has gone wrong at Intel, but I know that the bean counters, not tech or manufacturing is running the company now. The board is chock full of similar. The transition to bean counters started with Otellini, now they have as CEO a guy who was CFO at Ebay. Quite stunning. Wonder what Gordon Moore thinks? Andy and Bob Noyce must be spinning in their graves.

Whoey Louie wrote in news: snipped-for-privacy@googlegroups.com:

Did you stop to think that Intel is going to bypass the 7nm node entirely?

The reference I made was to IBM. TSMC and Samsung and IBM are making 7nm node chips together that look better than the process AMD went with. Mostly the same but slightly newer.

They look way cool. Like old sepia photos, only 'crisper'. hehe. Way 'crisper'.

Whoey Louie wrote in news:7bfb4c1d-998a-4bfb- snipped-for-privacy@googlegroups.com:

With 7nm just entering the market, it will take a few years to amortize the fab hardware costs.

Got a citation?

yeees. Ever seen a valve?

Yeah. There are better ways to handle that of course, but it does require a bit more complexity.

NT