Am 02.07.2018 um 21:24 schrieb Castorp:
Yes. I'm just playing with this one:
<because I'm sick of the low frequency noise of my FFT analyzer.
It is recommended to leave it alone for 2/3 of the conversion cycle, i.e no toggling of the conversion clock, no activity to read it out etc.
It requires a 100 MHz SPI clock or quite clumsy multi-cycle reading at 1 MHz sample rate.
regards, Gerhard
ised by the results I got for >=24 bit ADCs. Sigma-Delta still rules thou gh, but I don't think it's due to anything fundamental.
uency noise.
to be super careful with these babies.
I got pretty similar results for the 20 and 24-bit SAR ADCs by Linear. Didn 't get as far as the "32-bit", which just has a lofty digital filter to spe w out a few more bits above 24, which are semi-meaningful. These ADCs are i ndeed not so bad!
From the still-unpublished pot: AD7177-2 is the champion. Use external 5 V reference, external crystal, and disable the internal input buffers. Then i t puts you somewhere around 15 nVRMS/decade of 1/f noise. With a white nois e floor of 32 nV/sqrtHz, that sets the corner frequency around 0.05 Hz. Qui te impressive! It also has negligible offset drift and sub-ppm per degree g ain drift.
Cheers, Nikolai
Because it wasn't up/down, but rolled over after 256 clocks and started again from zero.
Well, you could feed it to an RC airplane servo.
Cheers
Phil Hobbs
-- Dr Philip C D Hobbs Principal Consultant ElectroOptical Innovations LLC / Hobbs ElectroOptics Optics, Electro-optics, Photonics, Analog Electronics Briarcliff Manor NY 10510 http://electrooptical.net http://hobbs-eo.com
t
y cycle when the counter has reached a value where the DAC is approximately equal to the input voltage. How could the bit stream output by the compar ator be duty cycle related to the input amplitude?
Ah, so the counter and DAC were generating a saw tooth waveform which was w orking with the comparator to create a pulse width modulated output.
In replay to Tom's "But it seems that the output is equivalent to delta sigma.", this is nothing like delta-sigma. This is simple pulse widt h modulation.
Yeah, that's pretty obvious now.
Rick C.
Typical SAR ADCs copy the input voltage onto a small capacitor, which is then disconnected from the input, and discharged with successively-smaller 1/2^n charge packets. What subsequently happens to the input during this conversion process doesn't matter.
--
Thanks,
- Win
Or the older ones, anyway -- I think today they're mostly two matched caps, pumped to VREF or GND alternately to successively divide the signal until done. I'd imagine JT can tell much more about it (well... "can" but not "may", as these things tend to be).
Possibly with a precision 2x gain stage at the same time, so the ref value doesn't change (as it does with a SAR + DAC + comparator), just the offset fed to the gain stage.
I'm pretty sure the XMEGA does it this way, at least -- when you set the ADC for higher gain settings, you have a selection in powers of 2, and each power adds another clock cycle to the acquisition. Or if you only need 8 bits of acquisition, then you only need as many cycles to do it. They also describe it as a pipelined ADC, which isn't relevant on the cheaper (D series) parts, but is on the fully-featured (A series) ones, which have multiple channels, and I guess, a greater amount of shared hardware, letting you interleave samples and such.
Tim
-- Seven Transistor Labs, LLC Electrical Engineering Consultation and Contract Design Website: https://www.seventransistorlabs.com/
So the capacitor charge goes to zero at end of SAR conversion ?
So when the next acquisition cycle begins, the charge is zero and it starts slowly to charge to the input voltage by integrating the charge? The charge is then isolated from input at the beginning of the hold period.
The interesting question is, is the analog input stage driver impedance so low, that it immediately changes the capacitor voltage, so at start of hold, the voltage is what happens to be at start of hold. Or is the driving impedance so high that the capacitor is actually integrating (averaging) the average voltage of the whole acquisition period ?
If it really averages the voltage level of the whole aquisition period, then this could be used to average out any very high noise, provided that the acquisition period is an exact integer multiple of the offending noise.
Compare this with some slow integrating ADCs with 10 Hz (100 ms) sampling rate, this handles nicely the mains hum in both 50 Hz or 60 Hz countries by integrating exactly 5 resp. 6 hum cycles during each cycle.
In this case the 500 kHz interference is well above Nyquist frequency, so the anti-alias filter should take care of the interface coming through the analog input pins, so the remaining noise comes through Vdd and ground pins.
If the acquisition could start at a specific 500 kHz cycle and last exactly an integer number of 500 kHz cycles before going to hold mode, much of the interference would be averaged out. The hold period could then last as long as is needed and then be idle until the next 500 kHz cycle and then start a new acquisition cycle.
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