add one resistor, quiet ugly smps ADC noise

The LTM8023 is a non-synchronous switcher, which doesn't have the giant spikes of a synchronous switcher. The switcher is a relatively slow NPN. All the nasty ground loops are internal to the brick. Used properly, it is very quiet.

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John Larkin         Highland Technology, Inc 

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John Larkin
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Single-point grounding is usually not practical. An ADC has an analog input, clock, power, and digital i/o. All of those have their own grounds. It doesn't help to add inductance to the adc chip's common.

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John Larkin         Highland Technology, Inc 

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John Larkin

Well, I did build diodes that worked from DC to nearly daylight (200 THz). ;)

But only one bit at a time.

Cheers

Phil Hobbs

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Dr Philip C D Hobbs 
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Phil Hobbs

It worked something like this.

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I may have clamped the summing node with some diodes. It's been a while.

I did a bunch of 16-bit DACs with discretes too. They drove a giant display in some military Dr Strangelove sort of thing.

I'be been lucky in working for companies with terrible marketing people who would take purchase orders for anything they could get.

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John Larkin         Highland Technology, Inc 

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John Larkin

I'm surprised you didn't use the BJT switches in inverted mode.

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Reply to
Winfield Hill

I did in my 16 bit DAC. Complementary over-driven emitter followers driving an r-2r ladder network. The simple NPNs were good enough for the 10 bit ADC.

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John Larkin         Highland Technology, Inc 
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John Larkin

Do modern designs still use SARs? It's been many years since I saw anything in print about them.

Of course I understood SAR and dual slope when I was a teenager but still don't really grasp delta sigma.

Reply to
Tom Del Rosso

Delta-sigma is fine for slow signals. For excellent resolution, it needs hefty oversampling, leading to long conversion times.

For quite fast sampling, SAR is OK; and for fast sampling, the way to go is a flash converter.

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Reply to
Tauno Voipio

It is easy to do the oversampling in delta sigma and can be done at many MH z. If you need MHz sample rate, then no, delta sigma is not the right tech nology. SAR can be done quite fast and these days there are very few true flash converters below some GHz. Instead of flash it is a hybrid of flash and SAR. It has some name that I can't recall at the moment.

Rick C.

Reply to
gnuarm.deletethisbit

Sure, there are lots of SAR ADCs around, up to 18 bits [1]. The three popular ADC architectures now are

SAR

Pipeline, which is multi-stage flash

Delta-sigma.

Dual-slope is rare nowadays. Capacitor DA is probably why.

Delta-sigma just uses a duty-cycle-based DAC to balance the input signal into an integrator. When it's balanced, the duty cycle tells you the input voltage. Some tricks are played to reduce the duty cycle ripple and speed things up.

[1] and some questionable claims of more.

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John Larkin         Highland Technology, Inc 

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John Larkin

So you adjust the duty until the integrator equals the input. But it seems that a "duty-cycle-based DAC" _is_ an integrator.

In the mid 80's Radio Shack sold only one ADC, an 8-pin DIP with an internal counter and DAC driving one input of a comparator, the output of which was a duty-cycle based digital value. No integrator. It looked cheap to me then. But it seems that the output is equivalent to delta sigma.

What is their "integrated digital filter?" That doesn't mean switched capacitor does it? I heard they are evil.

Reply to
Tom Del Rosso

The trick with delta sigma is that the scheme pushes the quantization noise out to higher frequency, where it's easy to filter out. (It's called 'noise shaping'.)

It slows down exponentially with the number of bits, like a V-F converter, but the tradeoff can be improved in lots of ways. A lot of clever people have worked on delta sigma converters--it's a bit of a cottage industry in EE departments.

Modern delta sigmas usually have multibit front ends like a pipeline converter, which helps the speed and also allows the use of dithering to get rid of idle tones. With a 1-bit converter, out-of-band dithering apparently makes a bit of a mess since there's no way to avoid overdriving the (1-bit) input quantizer.

Cheers

Phil Hobbs

(And no, I don't know how they work exactly either.)

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Phil Hobbs

Well, one sort of DAC is a precise digital duty cycle followed by a lowpass filter. We do that ourselves to make slow analog voltages, like for offset trims. We use a uP PWM channel, or make a PWM inside an FPGA. Once you're inside an FPGA, you can do delta-sigma instead of simple PWM.

(I don't entirely understand how high-precision delta-sigma ADCs or DACs work, specifically how they manage edge accuracy.)

No, they just do numerical filtering, probably just averaging, on the ADC's raw "24 bit" digital data. The 24 bit data claim is of course nonsense, because unfiltered it has 56 LSBs RMS noise.

You could get the same results by adding analog (dither) noise to the front-end of a 16 or 18 bit ADC, then averaging. Maybe that's what they do.

May as well buy a delta-sigma ADC and get the same precision for about a tenth the price.

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John Larkin         Highland Technology, Inc 
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Reply to
John Larkin

I don't think so. The DAC is a conventional DAC that converts the counter output to an analog voltage, right? Then that analog signal is compared to the analog input, right? That is a ultra slow linear counting version of a SAR. At the point the comparator trips the counter value is the digital output. Not at all equivalent to a delta sigma.

Rick C.

Reply to
gnuarm.deletethisbit

Disabling a converter through it's analog feedback path is indeed dependent on the converter's topology.

I sometimes question whether PFM type modulators or hysteritic controllers can really be considered to be stable, in the conventional sense. Like all bang-bang control schemes, they depend on the relatively slow response of the external environment to mimic a stable condition.

If enable lines weren't tied into other circuitry, they might be used for similar gating, however one should always be aware of the transient implications of such action, as they may create unintended surges in nodes of a PWM circuit.

RL

Reply to
legg

SAR is catching up fast, also in the higher number of bits. I was surprised by the results I got for >=24 bit ADCs. Sigma-Delta still rules though, but I don't think it's due to anything fundamental.

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More will be published later, including actual measurements of low-frequency noise.

One obvious thing I "discovered" along the way was that you really have to be super careful with these babies.

Cheers, Nikolai

Reply to
Castorp

It was an 8-pin DIP. The counter value wasn't output. All that was readable was the comparator output, so the output was the duty cycle.

Reply to
Tom Del Rosso

So there is a proper Sample & Hold in front of the SAR ? Without a S&H any SAR could produce quite erratic results, if the input varies during the SA sequence due to bad anti-aliasing filters or power supply noise.

Is the sample pulse synchronized with the converter cycle pulse ? This would at last give consistent measurements, although not quite "correct" values. Integrate & Dump in front would be even better.

Reply to
upsidedown

Think about this a bit. The output of the comparator will be 50/50 duty cy cle when the counter has reached a value where the DAC is approximately equ al to the input voltage. How could the bit stream output by the comparator be duty cycle related to the input amplitude?

How was this output to be used?

Rick C.

Reply to
gnuarm.deletethisbit

A SAR's analog input voltage is indeed held in a Sample & Hold. Although Maxim calls it a "track-and-hold."

73,
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Don Kuenz, KB7RPU

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