The plan was to clock the data register of the receiving FPGA at the middle of the 4ns data window, with 2 ns of margin both ways. Instead it got clocked at the edge, just about the time the data was changing. It's astounding that it usually worked; I had to freeze spray the ADC to break it reliably.
The ADC is the smaller BGA near the center, and the big chip is the FPGA. All the data and clocks are LVDS.
-- John Larkin Highland Technology, Inc picosecond timing precision measurement jlarkin att highlandtechnology dott com http://www.highlandtechnology.com
Den tirsdag den 20. juni 2017 kl. 00.44.47 UTC+2 skrev John Larkin:
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a eI'd say that was they right edge, the hold time on an FF is usually zero or slightly negative so you want to maximize the setup time and just make sure that the wire etc. delay on the clock is never longer than on the data
I2S has the same set of problems, in spades.
John Larkin wrote on 6/19/2017 6:44 PM:
It usually worked because the aperture time of an FPGA input is very short. It will only screw up when you cross that aperture. Clocking at about the time it changes will only make it fail if the data changes nearly on the aperture so some of the data changes before the aperture time and some changes after the aperture time. I don't know about the inputs compared to the internal FFs, but the alleged aperture windows of the FFs in a modern FPGA are supposed to in the fs range, but I should look that up as it has been a while since I read it. My browser isn't working at the moment.
-- Rick C
That LTC2242 ADC outputs a regenerated clock that matches the data timing, all LVDS, so you don't have to worry about the relative timing from the FPGA clock out to the ADC data coming back in. That helps enormously. All the ADC-related logic is clocked from the ADC itself.
-- John Larkin Highland Technology, Inc lunatic fringe electronics
Worse ones. There are real hang-ups that sometimes require "banging the bus" or a power-cycle. So far I didn't have that with SPI and I used SPI a lot more than I2C, mostly much for that reason.
-- Regards, Joerg http://www.analogconsultants.com/
yeh one wrong glitch on I2C and you are stuck forever. afaiu that is one of the reasons for SMBus used on PC motherboards etc. it is basically I2C with a minium speed and a timeout
I2S I2C
But your point is well taken. SPI is a lot easier to route than I2C, as well. Makes sense because SPI isn't a standard at all (make it what you want), where I2C is limited by design/specification.
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