So we had a bit of a layout screwup with an SPI ADC: the apparently very nice ADC122S625 dual 12-bit simultaneous-sampling, differential-input serial ADC. How bad a screwup? Well, the output has like 20 LSBs of junk on it. Blech.
Weirdly, the junk is highly level-dependent. It's much less at outputs near zero and gets steadily worse towards half-scale.
My theory is that the SDO pin is coupling through into the sampled input somehow, so that the change in the bit pattern is what's causing the difference. The conversion is clocked by SCLK, so transitions in the higher bits on SDO would cause errors earlier in the conversion, leading to worse noise.
The solution would appear to be to put the analogue inputs in a Faraday cage made of pours, the way you do with SMPS wiring.
Or am I nuts? It's supposed to be a _sampling_ ADC after all!
Cheers
Phil Hobbs