AD7793 again

I actually live within a few miles of the Analog Devices corporate headquarters south of Boston.

You want me to go over there and ask someone about it?

I'm only half kidding.

Ahh, pick another ADC. Re: ESD and current through the diodes, Well if it's low power then were's the current go? Do you have to build in zeners and R's that turn on?

George H.

Yup, TI. TI understands digital better.

ADI says that the ESD diodes protect the chip from damage in "handling and production" namely when it's not being used.

They also suggest that the chip can latch up (which is generally destructive) from about a 100 mA ESD diode spike.

Holy cow.

I would find a different chip.

Beats me.

Don't count on it! They had a very similar problem with their 5000 series DSPs. If the I2S interface lost a clock, the channels were off by one until the next system reset. Very ugly, since it happened every half hour or so.

Yeah, not good. I'll have to check the ADCs we're using again.

--Keith

Sounds unlikely. There has to be some kind of hard reset - it's not as if Analog Devices can manufacture it in a well-defined initial state.

This is true of pretty most ESD diodes - they work by diverting current into the substrate and once it gets into the substrate it can come out anywhere.

They aren't designed to let you operate the device outside of specification, but rather to prevent it from blowing up if some input get outside of specification.

That suggests that you aren't doing absolutely everything right. It's only got 16 pins. Have you looked at each one of them, and made sure that the voltage and impedances conform to what's called p up by the data sheet?

I know that this is teaching my grandmother to suck eggs, but lots of this kind of problem gets solved when somebody notices that something that was "obviously okay" turns out to be subtly wrong.

It's a problem if you don't know about it. I first ran into it in 1979, but if you think about where the current is going after it's been diverted by an ESD diode, it's fairly obvious that it is at liberty to mess up the rest of the circuit.

Jim Thompson could probably tell us why it's expensive to provide ESD protection any other way.

Where does it say that? Page 7,8?

Maybe all spice models used by chip design engineers should have a built-in ( and unremoveable ) system which produces random 1 Kv and 1 ns spikes on every input and output line. Then the people using the models would have something like a real world situation to cope with.

Pages 2 and 3 talk about corrupting registers if the analog inputs touch the ESD diodes. The data sheet mentions this, too.

We've been testing pretty hard, and we are not banging the ESD diodes or violating any obvious limits or timings. But if we run the temperature down to -5 or -10C, the chip gets confused and outputs gibberish, and warming it up doesn't fix it. It needs the reset sequence.

That's what's so insane: one glitch or temperature excursion, and the SPI interface gets and stays confused. CS seems to connect and disconnect the pins, but deselecting the chip initializes no internal states or counters.

"Faraday shield" is mentioned twice in this FAQ. "Corrupt" appears 8 times.

The last paragraph on page 2 is ominous. Blame the customer.

They do normally test the first silicon of each new chip design for both ESD robustness and also latchup.

As for catching it at the simulation stage, a big part of the problem is that the spice models are fitted against measurements so that they match the measured characteristics very well, but the measurements are usually only done within a range of "reasonable" voltages and currents, certainly not up to 1kV. The device models do not necessarily behave like the real devices under ESD conditions, and the designers know this. Therefore they often get their ESD cells from a corporate "ESD group" who are supposed to know all about this stuff somehow - perhaps by some experiments. From the circuit designer's point of view, as long as they have used the corporate standard cell they would be mostly off the hook in the event of reliability problems due to ESD. Sometimes the standard ESD cells limit performance too much (capacitance etc.) and the circuit designer will have to do their own ones, in which case they would take much more interest in the actual robustness, and probably do a lot of extra testing on the first silicon.

Also substrate currents from the ESD diodes can be collected by placing a thick wall of grounded substrate contacts around the ESD cell. Potential latchup candidates can be kept away from ESD diodes. (e.g. grounded n-well capacitors close to a vertical NPN with its base biased positively is a PNPN SCR structure, as are most CMOS logic gates.) Some designers know about these things, but sometimes management dictates that the designer can't do their own layout and a layout engineer is responsible for that. Often the people doing the layout don't know any electronics but they may or may not have been given rules that may help to prevent latchup hazards. When debugging a chip on a probe station, it is usually easy to trigger any latchup hazards using a pulsed laser (which is often fitted to the microscope because it is used for cutting tracks etc.). If the laser is de-focussed (to prevent cutting anything) and then fired at a part of the chip, it will inject carriers and trigger any latchup hazards in that region. By going around a chip looking for these, I was able to fix most of them one by one such that eventually it was much harder to latch up the chip. I don't think it is normally something people bother with, provided the chip passes the test where they try to latch it up by injecting currents into the external pins.

I thought ESD diodes were to prevent damage during standard low ESD producing handling? If the part is in a circuit, where could the abnormal voltage be coming from?

I have seen a few parts that provide a spec on how much current is allowed into inputs during operation, but otherwise, why would anyone think that is an ok thing to do?

Burst and surge transients

Internal EMC noise

Overshoots from converters

Conducted noise from external signals

Radiated noise from other devices

etc

Cheers

Klaus

I have seen this sort of thing when the SPI is wrongly configured, so it is sampled on the wrong clock edge say (i.e. during a transition). Then a temperature change speeds things up or slows them down and it goes wrong.

"warming it up doesn't fix it" is strange but perhaps its configuration registers get written to accidentally? Do you write to the chip continually or just at startup?

There was a case of peculiar latchup, let's see, it was the Raspberry Pi board. When photographing it with flash, the power supply would conk out.

Turns out, by masking off everything but the PSU controller (which happened to be a CSP thing), it would still fail, and masking that one part, it was fine.

EMC is sometimes more than just "low bandwidth" (up to ~GHz) electrical signals!

Tim

It seems software people are particulary plagued by this type of thinking. They never think about what happens to their design if something UNEXPECTED happens.

Blue screen death should be unaccepable

try a small RC low pass filter on the clock pin to stop any glitches on the clock from counting as an extra edge.

Aren't all these design issues? They all sound like reasons to respin a board with more protection. I know the stuff I have built had specs on what it had to withstand and I never depended on poorly specified ESD diodes for protection.

You didn't really answer the question. Why would you expect the ESD diodes to protect the part while in use without problems?

Lots of people have confirmed that our timing is correct. Tweaking clock and data ehges with capacitors is the usual way to spot marginal timing, and that does nothing to the error rate.

We initialize it once at startup, run it in continuous mode, and read it out now and then. The data sheet and FAQ make it clear that if it ever once misses one clock count, it's hosed thereafter. Deasserting CS does not initialize anything in the SPI interface.

The clock input is claimed to be Schmitted. Using a fast fet probe at the clock input, it looks fine.

We tried adding 75 pF caps to clock, then data lines, to push the timing left and right; no better.