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- Subject
- Posted on
- Winfield Hill
November 9, 2016, 7:00 pm
Anybody care to speculate about the most important aspects to consider when
trying to achieve 98% efficiency in a low-power (20mW) boost converter? Most
available step-up converter circuits seem to perform in the 85 to 90% region.
I'm finishing a PCB "test bed" layout, which allows jumper-selection of
different inductors, synchronous switches, and adjustable controller parameters.
I'm hoping not to forget something important before sending it off to the PCB
house. Just for fun I thought I'd make it in the form of an Arduino shield;
giving an option for the processor to control the parameters and take
measurements.
trying to achieve 98% efficiency in a low-power (20mW) boost converter? Most
available step-up converter circuits seem to perform in the 85 to 90% region.
I'm finishing a PCB "test bed" layout, which allows jumper-selection of
different inductors, synchronous switches, and adjustable controller parameters.
I'm hoping not to forget something important before sending it off to the PCB
house. Just for fun I thought I'd make it in the form of an Arduino shield;
giving an option for the processor to control the parameters and take
measurements.
--
Thanks,
- Win
Thanks,
- Win
Re: Achieving 98% efficiency in a boost converter
For this board my first two guesses would be switches' gate charge losses and the inductor's DCR.
Sounds like a cool project!
Re: Achieving 98% efficiency in a boost converter
Sadly, your approach has an irony: the jumpers will add leakage inductance,
which you'll have to identify as a source of loss. :-(
The quiescent current of the control circuit itself will be a considerable
fraction of that, even for very-fine-feature-size ICs. Perhaps there are
some energy-harvesting controllers that idle that low, but gee.
Is this from scratch, or testing commercial ICs?
Note that a synchronous converter needs to be very closely tuned. Nearly
zero dead time. No time to let body diodes conduct (that's loss, and
probably step recovery behavior too), no time to draw shoot-through current
(which you'll want to assist by adding supply inductance). Few commercial
controllers and regulators are designed this way, instead using a cautious
~30ns or so.
Tim
which you'll have to identify as a source of loss. :-(
The quiescent current of the control circuit itself will be a considerable
fraction of that, even for very-fine-feature-size ICs. Perhaps there are
some energy-harvesting controllers that idle that low, but gee.
Is this from scratch, or testing commercial ICs?
Note that a synchronous converter needs to be very closely tuned. Nearly
zero dead time. No time to let body diodes conduct (that's loss, and
probably step recovery behavior too), no time to draw shoot-through current
(which you'll want to assist by adding supply inductance). Few commercial
controllers and regulators are designed this way, instead using a cautious
~30ns or so.
Tim
--
Seven Transistor Labs, LLC
Electrical Engineering Consultation and Contract Design
Seven Transistor Labs, LLC
Electrical Engineering Consultation and Contract Design
We've slightly trimmed the long signature. Click to see the full one.
Re: Achieving 98% efficiency in a boost converter
The Baxendall Class-D oscillator is self-resonant, so doesn't have to be "closely tuned" and switches when there is zero current through the switches, eliminating switching losses.
In the rudimentary MOS-FET-driven version
http://sophia-electronica.com/Baxandall_parallel-resonant_Class-D_oscillator1.htm
about the only place to waste power is in the damping resistors on the MOS-FET gates, and the series resistance of the inductor and the transformer windings.
Keeping those losses low might bulk up the cores a bit.
Leakage inductance doesn't come into it
I've no idea whether it could make 98%, but Jim Williams got close to 95% with messier and cheaper circuits.
You might have have floating windings to drive synchronous inverter switches on the output, and might all end up a bit bulkier than Win has in mind.
--
Bill Sloman, Sydney
Bill Sloman, Sydney
Re: Achieving 98% efficiency in a boost converter
On Wednesday, November 9, 2016 at 6:54:04 PM UTC-5, Winfield Hill wrote:
Too many degrees of freedom to answer you Win--it depends very much on
the Vout/Vin ratio, for one, and the absolute values of Vin and Vout,
too.
E.g., I designed a 3uW boost (0.6-to-3V @ 1uA). I had to use all jelly-bean
discretes since there were no Iq-suitable ICs, and BJTs due to the low
input voltage. Efficiency was ~70%, IIRC.
Where the input voltage is low and currents high, switch saturation voltage
is limiting. Where the output voltage is low, rectification losses are a
pain; a Schottky diode's 5% loss was usually better than a synchronous
rectifier at 6V output, after switching losses and rectifier drive and
added complexity to gain perhaps 2% extra efficiency were factored in.
Breaking your problem into pieces, fundamentally, getting 98% overall
efficiency is a matter of storing over 99% of the input energy in the
inductor each time you charge it, and delivering over 99% of the
stored energy to the load each flyback cycle.
Reducing further, charging, the inductor has to store at least 99 times
the switch's gate drive, switching loss, and conduction losses. The
inductor's d.c.r. loss factors in too. Core losses were minor, IME.
The same analysis can be applied to the flyback portion of the cycle, and
the 2% loss budget can be distributed across the two phases as you see
fit.
I suspect you'll find your parameters produce optimal efficiency with
MOSFET switches infrequently operated, large-cored high-valued inductors,
short bursts or single-cycles of activity, and long periods quiescent.
But YMMV.
I hope these musings are of some use...
Cheers,
James Arthur
Too many degrees of freedom to answer you Win--it depends very much on
the Vout/Vin ratio, for one, and the absolute values of Vin and Vout,
too.
E.g., I designed a 3uW boost (0.6-to-3V @ 1uA). I had to use all jelly-bean
discretes since there were no Iq-suitable ICs, and BJTs due to the low
input voltage. Efficiency was ~70%, IIRC.
Where the input voltage is low and currents high, switch saturation voltage
is limiting. Where the output voltage is low, rectification losses are a
pain; a Schottky diode's 5% loss was usually better than a synchronous
rectifier at 6V output, after switching losses and rectifier drive and
added complexity to gain perhaps 2% extra efficiency were factored in.
Breaking your problem into pieces, fundamentally, getting 98% overall
efficiency is a matter of storing over 99% of the input energy in the
inductor each time you charge it, and delivering over 99% of the
stored energy to the load each flyback cycle.
Reducing further, charging, the inductor has to store at least 99 times
the switch's gate drive, switching loss, and conduction losses. The
inductor's d.c.r. loss factors in too. Core losses were minor, IME.
The same analysis can be applied to the flyback portion of the cycle, and
the 2% loss budget can be distributed across the two phases as you see
fit.
I suspect you'll find your parameters produce optimal efficiency with
MOSFET switches infrequently operated, large-cored high-valued inductors,
short bursts or single-cycles of activity, and long periods quiescent.
But YMMV.
I hope these musings are of some use...
Cheers,
James Arthur
Re: Achieving 98% efficiency in a boost converter, inducement
Thanks, your comments are right on target and can kick
off the discussion I was hoping to see. I'll get into
that conversation tomorrow. But in the meantime I've
updated my draft schematic and PCB layout, adding more
features and items relevant to the discussion.
https://www.dropbox.com/sh/aj1tlto0fa6w6ty/AADJ9BWmCQE_ed7NHp60PgMja?dl=0
Here's an inducement: anyone who'd like to experiment
with issues and concepts embedded in the RIS-767
board, I'll send you two blank PCBs to play with.
You just have to talk about what you learn, should
you get around to learning anything!
--
Thanks,
- Win
Thanks,
- Win
Re: Achieving 98% efficiency in a boost converter, datasheets
On Saturday, November 12, 2016 at 7:06:58 AM UTC-5, Winfield Hill wrote:
You're going to wind up with a while bunch of trade-offs, such as larger and
larger FETs reduce conduction loss, but take more power to drive;
higher inductance lowers i^2*r losses from peak currents, but increases
the parasitic capacitance you have to drive, etc.
I designed a ~120W two-stage switcher a couple years ago where maximum
efficiency was essential for heat management, as the unit was in still
air in a small, sealed box, & subject to heating by direct sunlight. I
wrote a spreadsheet to model the losses given the various parameters,
which helped me choose FETs & make other decisions. A little messy and
crude, but predicted actual losses quite accurately.
At 20mW you'll have the advantage of almost ideal capacitors and plenty
of capacitance for storage.
At Rds(on)=.065 ohms, the FDN337 looks like overkill.
Please pardon me as I doodle here...
A few calculations:
1) Conduction loss. For 20mW @ n98%%, total loss budget is 400uW. Assuming
Vin=4V and n98%%, i.in(avg)=5mA; i^2 * Rds(on) = 1.6uW for a perfect,
zero-ripple-current infinitely-fast continuous-mode switcher, or four
times that for a boundary-mode design with twice the peak iL.
2) Gate drive loss: If the gate charge is 7nC driven at 4V, and we start
off allocating it 1/10th the total loss budget...that's 40uW @ 4V, or
10uA(avg), which means we could afford to drive it at f=i/2q70%0Hz. Ballpark.
3) Output capacitance: Assuming Vout=8V (I don't know the actual), 20mW is
2.5mA load. For 50mV output ripple and 700Hz update rate, we calculate
the necessary filter cap:
C = i * dt / dV = 2.5mA*(1/700)s / 50mV = 70uF.
4) If we budgeted a maximum permissible conduction loss, i^2 * ( Vds(on) +
dcr(L) ), that fixes a max. peak current i.pk. From i.pk and Vin and our
output ripple voltage spec. and the output capacitance, we can compute
the minimum inductor value. The inductor value and i.pk then give us
the inductor charging time, i.e., the switch on-time.
Interesting--the ripple voltage depends ultimately on the available
output capacitance. After picking a maximal practical capacitor, given
the output capacitance available, the maximum allowable output ripple
voltage, and the inductor value, you can calculate the peak inductor
current needed for any given switching frequency, and from that, the FET
conduction losses.
98% is going to be fun!
Cheers,
James Arthur
You're going to wind up with a while bunch of trade-offs, such as larger and
larger FETs reduce conduction loss, but take more power to drive;
higher inductance lowers i^2*r losses from peak currents, but increases
the parasitic capacitance you have to drive, etc.
I designed a ~120W two-stage switcher a couple years ago where maximum
efficiency was essential for heat management, as the unit was in still
air in a small, sealed box, & subject to heating by direct sunlight. I
wrote a spreadsheet to model the losses given the various parameters,
which helped me choose FETs & make other decisions. A little messy and
crude, but predicted actual losses quite accurately.
At 20mW you'll have the advantage of almost ideal capacitors and plenty
of capacitance for storage.
At Rds(on)=.065 ohms, the FDN337 looks like overkill.
Please pardon me as I doodle here...
A few calculations:
1) Conduction loss. For 20mW @ n98%%, total loss budget is 400uW. Assuming
Vin=4V and n98%%, i.in(avg)=5mA; i^2 * Rds(on) = 1.6uW for a perfect,
zero-ripple-current infinitely-fast continuous-mode switcher, or four
times that for a boundary-mode design with twice the peak iL.
2) Gate drive loss: If the gate charge is 7nC driven at 4V, and we start
off allocating it 1/10th the total loss budget...that's 40uW @ 4V, or
10uA(avg), which means we could afford to drive it at f=i/2q70%0Hz. Ballpark.
3) Output capacitance: Assuming Vout=8V (I don't know the actual), 20mW is
2.5mA load. For 50mV output ripple and 700Hz update rate, we calculate
the necessary filter cap:
C = i * dt / dV = 2.5mA*(1/700)s / 50mV = 70uF.
4) If we budgeted a maximum permissible conduction loss, i^2 * ( Vds(on) +
dcr(L) ), that fixes a max. peak current i.pk. From i.pk and Vin and our
output ripple voltage spec. and the output capacitance, we can compute
the minimum inductor value. The inductor value and i.pk then give us
the inductor charging time, i.e., the switch on-time.
Interesting--the ripple voltage depends ultimately on the available
output capacitance. After picking a maximal practical capacitor, given
the output capacitance available, the maximum allowable output ripple
voltage, and the inductor value, you can calculate the peak inductor
current needed for any given switching frequency, and from that, the FET
conduction losses.
98% is going to be fun!
Cheers,
James Arthur
Re: Achieving 98% efficiency in a boost converter, datasheets
On Saturday, November 12, 2016 at 8:40:48 AM UTC-5, snipped-for-privacy@yahoo.com wrote:
Oh, I forgot to factor in that FET conduction losses are reduced by the
duty factor, both for the main switch and the synchronous rectifier;
dcr(L) matters twice, both for charging and discharging.
All this doodling suggests the start of a spreadsheet to me with Vin,
Vout, n, P, Vripple, Rds(on), Qg, dcr(L), and a few other inputs...
Cheers,
James Arthur
Oh, I forgot to factor in that FET conduction losses are reduced by the
duty factor, both for the main switch and the synchronous rectifier;
dcr(L) matters twice, both for charging and discharging.
All this doodling suggests the start of a spreadsheet to me with Vin,
Vout, n, P, Vripple, Rds(on), Qg, dcr(L), and a few other inputs...
Cheers,
James Arthur
Re: Achieving 98% efficiency in a boost converter, datasheets
snipped-for-privacy@yahoo.com wrote...
I'm sorry for not yet taking the time to introduce
and discuss my project in more detail. I'm still
postponing that, but will say a few quick things:
1) My initial and primary goal is to optimize a
2.0 to 2.4-volt boost converter running at 10mA,
or 24mW, with no more than 0.5mW of loss. For
that purpose the small TS5A3159 spdt switch,
0.8 ohms and low capacitance, should be good.
There are also even smaller parts in the same
sot-23 package layout.
2) Other choices on the PCB are to allow for
playing around with higher optimal currents.
I figured, once the generalized PWM hardware
was in place, why not add a provision for
larger switches and inductors. I'm going to
add to the discrete MOSFET footprint choices.
3) Since this is just a test-bed breadboard,
I separated the power consumption for PWM
control and driving FETs, from the inductor
and switch losses. The switch losses still
include f C V^2 of switch capacitance loss,
but not the gate-driving power consumption.
4) I'm still looking hard for good inductor
candidates to add to the PCB. Most have
appallingly-high losses, and unfortunately
these are not detailed on their datasheets.
I'm sorry for not yet taking the time to introduce
and discuss my project in more detail. I'm still
postponing that, but will say a few quick things:
1) My initial and primary goal is to optimize a
2.0 to 2.4-volt boost converter running at 10mA,
or 24mW, with no more than 0.5mW of loss. For
that purpose the small TS5A3159 spdt switch,
0.8 ohms and low capacitance, should be good.
There are also even smaller parts in the same
sot-23 package layout.
2) Other choices on the PCB are to allow for
playing around with higher optimal currents.
I figured, once the generalized PWM hardware
was in place, why not add a provision for
larger switches and inductors. I'm going to
add to the discrete MOSFET footprint choices.
3) Since this is just a test-bed breadboard,
I separated the power consumption for PWM
control and driving FETs, from the inductor
and switch losses. The switch losses still
include f C V^2 of switch capacitance loss,
but not the gate-driving power consumption.
4) I'm still looking hard for good inductor
candidates to add to the PCB. Most have
appallingly-high losses, and unfortunately
these are not detailed on their datasheets.
--
Thanks,
- Win
Thanks,
- Win
Re: Achieving 98% efficiency in a boost converter, datasheets
Jim Thompson wrote...
So far measuring commercial inductors, that's
all I've come up with. Most have unacceptable
losses at high frequencies. One that should
work is a TDK SL1720, a large 17mm D x 20mm H
size. The 1.5mH part is rated at 1 amp, and
DCR = 0.86 ohms. Its AC resistance measures
3 ohms at 20kHz. With D = 17% and ON time
8.4us, dI = 8.4us 2.0V/1.5mH = 11 mApp, and
the I^2 R loss would be about 0.125W, or 0.6%
of my 24mW power. Wait, that seems too low.
I'd like to be able to scale this to higher
frequencies, e.g. 100uH at 300kHz. Could
be, I have some candidate parts to test.
So far measuring commercial inductors, that's
all I've come up with. Most have unacceptable
losses at high frequencies. One that should
work is a TDK SL1720, a large 17mm D x 20mm H
size. The 1.5mH part is rated at 1 amp, and
DCR = 0.86 ohms. Its AC resistance measures
3 ohms at 20kHz. With D = 17% and ON time
8.4us, dI = 8.4us 2.0V/1.5mH = 11 mApp, and
the I^2 R loss would be about 0.125W, or 0.6%
of my 24mW power. Wait, that seems too low.
I'd like to be able to scale this to higher
frequencies, e.g. 100uH at 300kHz. Could
be, I have some candidate parts to test.
--
Thanks,
- Win
Thanks,
- Win
Re: Achieving 98% efficiency in a boost converter, datasheets
On Sunday, November 13, 2016 at 1:33:37 AM UTC+11, Winfield Hill wrote:
<snip>
The usual way of getting a better inductor is to wind your own, but manufacturers are better at doing banked (low capacitance) windings.
And your foot-print is a bit on the small side to offer you much choice of ferrite.
<snip>
The usual way of getting a better inductor is to wind your own, but manufacturers are better at doing banked (low capacitance) windings.
And your foot-print is a bit on the small side to offer you much choice of ferrite.
--
Bill Sloman, Sydney
Bill Sloman, Sydney
Re: Achieving 98% efficiency in a boost converter, datasheets
On Saturday, November 12, 2016 at 3:33:37 PM UTC+1, Winfield Hill wrote:
I think the problem is ill-defined. When the only
requirement is efficiency, a boost converter can
be made as simple, large and expensive as anybody
sees fit.
Without the size restriction one could go to a
very low switching frequency, ruling out all switching
losses. Conduction loss at low frequencies is a
problem of cost (amorphous iron, film caps), and size
(put components in parallel).
The power needed for the controller goes away when
you don't add it (no specs. given on that).
There are peculiar effects that still might make
optimization interesting. E.g. losses of an
inductor are lowest around 85 deg C, and diode
losses go down with temperature.
-marcel
I think the problem is ill-defined. When the only
requirement is efficiency, a boost converter can
be made as simple, large and expensive as anybody
sees fit.
Without the size restriction one could go to a
very low switching frequency, ruling out all switching
losses. Conduction loss at low frequencies is a
problem of cost (amorphous iron, film caps), and size
(put components in parallel).
The power needed for the controller goes away when
you don't add it (no specs. given on that).
There are peculiar effects that still might make
optimization interesting. E.g. losses of an
inductor are lowest around 85 deg C, and diode
losses go down with temperature.
-marcel
Re: Achieving 98% efficiency in a boost converter, datasheets
On Sun, 23 Apr 2017 00:16:09 -0700 (PDT), snipped-for-privacy@iae.nl wrote:
<snip>
Core loss data, at the low flux levels required here, would be
exceptionally difficult to collect.
Extrapolating from the published charts by two orders of magnitude in
one direction is a somewhat wishful expedient, as the charts
themselves only use straight line approximations for the actual curves
generated by empirical data and modeling.
Core loss equation exponents actually shift with each order of
magnitude of both frequency and flux density. At low power, worst case
losses might be expected to occur at lower ambient temperature due to
published high flux ntc below 60-85C, but this information is not
actually available at lower flux levels.
Low-power-circuit efficiency differs from low power efficiency in
medium-power circuits, as you point out, because it should profoundly
affect the choice of topology. It's not just a matter of smaller
parts. Characterizing the source impedance can be important in making
such decisions, as decoupling can only go so far in masking it.
RL
<snip>
Core loss data, at the low flux levels required here, would be
exceptionally difficult to collect.
Extrapolating from the published charts by two orders of magnitude in
one direction is a somewhat wishful expedient, as the charts
themselves only use straight line approximations for the actual curves
generated by empirical data and modeling.
Core loss equation exponents actually shift with each order of
magnitude of both frequency and flux density. At low power, worst case
losses might be expected to occur at lower ambient temperature due to
published high flux ntc below 60-85C, but this information is not
actually available at lower flux levels.
Low-power-circuit efficiency differs from low power efficiency in
medium-power circuits, as you point out, because it should profoundly
affect the choice of topology. It's not just a matter of smaller
parts. Characterizing the source impedance can be important in making
such decisions, as decoupling can only go so far in masking it.
RL
Re: Achieving 98% efficiency in a boost converter, datasheets
On Sunday, April 23, 2017 at 5:41:44 PM UTC+2, legg wrote:
Why do you think the flux level is low (I agree it would be
the case for high efficiency)? If we make the core smaller, flux
levels will increase. Although the flux level would decrease for
bigger cores, the volume of magnetic material increases and may
drive up the loss again. Without a size (and EMI) restriction one
would use an air-core :-)
-marcel
Why do you think the flux level is low (I agree it would be
the case for high efficiency)? If we make the core smaller, flux
levels will increase. Although the flux level would decrease for
bigger cores, the volume of magnetic material increases and may
drive up the loss again. Without a size (and EMI) restriction one
would use an air-core :-)
-marcel
Re: Achieving 98% efficiency in a boost converter, datasheets
On Mon, 24 Apr 2017 03:10:47 -0700 (PDT), snipped-for-privacy@iae.nl wrote:
I think it's a physical scaling thing caused by the winding, that
limits the core size reduction. Winding length decreases linearly, but
xsectional area decreases by the square....
RL
I think it's a physical scaling thing caused by the winding, that
limits the core size reduction. Winding length decreases linearly, but
xsectional area decreases by the square....
RL
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