A problem for which I have no clue...

A problem for which I have no clue...

Recover CARRIER FREQUENCY ONLY, no data requirements, from...

QPSK, 16-QAM, and higher order.

Ideas? Pointers? Something I can buy off-the-shelf would be fine.

Thanks! ...Jim Thompson

-- | James E.Thompson | mens | | Analog Innovations | et | | Analog/Mixed-Signal ASIC's and Discrete Systems | manus | | San Tan Valley, AZ 85142 Skype: skypeanalog | | | Voice:(480)460-2350 Fax: Available upon request | Brass Rat | | E-mail Icon at

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| 1962 | I love to cook with wine. Sometimes I even put it in the food.

Reply to
Jim Thompson
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Costas loop?

Jeroen Belleman

Reply to
jeroen Belleman

What's the frequency?

The carrier phase is of course ambiguous, unless you have some occasional intervals of single-phase (unmodulated) signal.

--

John Larkin         Highland Technology, Inc 
picosecond timing   laser drivers and controllers 

jlarkin att highlandtechnology dott com 
http://www.highlandtechnology.com
Reply to
John Larkin

Around here, that is a part of town where there are a bunch of spas.

Reply to
DecadentLinuxUserNumeroUno

I think that will only handle DPSK, and not higher, without enormous embellishment. ...Jim Thompson

--
| James E.Thompson                                 |    mens     | 
| Analog Innovations                               |     et      | 
| Analog/Mixed-Signal ASIC's and Discrete Systems  |    manus    | 
| San Tan Valley, AZ 85142     Skype: skypeanalog  |             | 
| Voice:(480)460-2350  Fax: Available upon request |  Brass Rat  | 
| E-mail Icon at http://www.analog-innovations.com |    1962     | 
              
I love to cook with wine.     Sometimes I even put it in the food.
Reply to
Jim Thompson

70MHz, phase immaterial, application is proprietary. All I need is a VCXO locked to the carrier frequency. ...Jim Thompson
--
| James E.Thompson                                 |    mens     | 
| Analog Innovations                               |     et      | 
| Analog/Mixed-Signal ASIC's and Discrete Systems  |    manus    | 
| San Tan Valley, AZ 85142     Skype: skypeanalog  |             | 
| Voice:(480)460-2350  Fax: Available upon request |  Brass Rat  | 
| E-mail Icon at http://www.analog-innovations.com |    1962     | 
              
I love to cook with wine.     Sometimes I even put it in the food.
Reply to
Jim Thompson

Looks possibly like some squaring loop (maybe 4X) will do the trick. ...Jim Thompson

--
| James E.Thompson                                 |    mens     | 
| Analog Innovations                               |     et      | 
| Analog/Mixed-Signal ASIC's and Discrete Systems  |    manus    | 
| San Tan Valley, AZ 85142     Skype: skypeanalog  |             | 
| Voice:(480)460-2350  Fax: Available upon request |  Brass Rat  | 
| E-mail Icon at http://www.analog-innovations.com |    1962     | 
              
I love to cook with wine.     Sometimes I even put it in the food.
Reply to
Jim Thompson

Limiter --> quadrupler --> PLL?

Or more generally, N-tupler for N equal phase states.

Tim

-- Seven Transistor Labs Electrical Engineering Consultation Website:

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"Jim Thompson" wrote in message news: snipped-for-privacy@4ax.com...

Reply to
Tim Williams

Looks like that is the requirement. I'm not conversant in these wild-ass modulation schemes. I'm working with a PhD who actually seems to know what he's doing, but can't design circuits >:-}

If he can verbalize the process I can design the circuit. ...Jim Thompson

-- | James E.Thompson | mens | | Analog Innovations | et | | Analog/Mixed-Signal ASIC's and Discrete Systems | manus | | San Tan Valley, AZ 85142 Skype: skypeanalog | | | Voice:(480)460-2350 Fax: Available upon request | Brass Rat | | E-mail Icon at

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| 1962 | I love to cook with wine. Sometimes I even put it in the food.

Reply to
Jim Thompson

I can verbalize it for you Consider qpsk, it has 4 phases 90 deg apart. If you put the signal through a 4x multiplier, then The phase changes get multiplied by 4 as well So now they are 360 deg changes, which means The modulation has been removed. In other words, if you put qpsk through A 4x multiplier, you will recover a carrier at 4x the carrier. It will be jittery however And will need smoothing.

Mark

Reply to
makolber

If these are all self-clocked serial schemes, a general detection apparatus might (1) start a time/amplitude converter (TAC) on one symbol, (2) stop the TAC on a second symbol. Digitize, of course. Then you prepare a big histogram of the time delays, and match the histogram peaks to integer-multiple-of-clock-times.

The trick, is to find a trigger scheme to detect a clear time-of-signal-occurrence appropriate to the 'higher order' modulations.

Reply to
whit3rd

IIRC, a Costas loop has four stable locking phases, so QPSK should still work. Reasonable higher-order modulation schemes code the data to make sure that there is enough energy in all the right places in the spectrum to achieve a stable lock. If that isn't guaranteed in your case, then well...

Jeroen Belleman

Reply to
Jeroen Belleman

I'd look at the use of an FPGA

Altera has one that's fairly cheap and VERY easy to use, the CYCIII, EP3C5, [unless you're brave, stay away from ball grid] runs up to 200MHz and even as high as 300MHz. Built-in 20 PLL and logic to spare, even a built- in FFT package. In other words, once get carrier, can do a LOT more.

The idea is to hit this problem with a sledge hammer, because the minute you solve the 'simple' problem for this PhD, he'll think of, "just one more thing to try." and an FPGA will enable him to play with the hardware using formulas.

If you're used to FPGA, grab the docs and have at it. If not, let the FAE do it for you.

Altera sells a devvelopment board, at cost, so you can get your feet wet without spending too much, just takes a PC to run it and their SW. I believe it uses HDML language but forgot now.

Why Altera? They had the BEST FAE's. I have a CYCIII development board and attended one of their classes. And, most importantly, Altera's FPGA does what you program. I was very surprised that for some suppliers that was NOT true. [Imagine fighting a DOUBLE debug problem!] When I investigated Xilinx XAUI stuff, the latency ate me alive, so couldn't use that family.

Reply to
RobertMacy

I think that _anything_ that'll handle 16-QAM and complexer will require your "enormous embellishment". It's kind of inherent in the problem statement.

--

Tim Wescott 
Wescott Design Services 
http://www.wescottdesign.com
Reply to
Tim Wescott

Maybe, maybe not. I only need carrier _frequency_, I don't need it coherent with data... I'm not demodulating, just grabbing frequency information. ...Jim Thompson

--
| James E.Thompson                                 |    mens     | 
| Analog Innovations                               |     et      | 
| Analog/Mixed-Signal ASIC's and Discrete Systems  |    manus    | 
| San Tan Valley, AZ 85142     Skype: skypeanalog  |             | 
| Voice:(480)460-2350  Fax: Available upon request |  Brass Rat  | 
| E-mail Icon at http://www.analog-innovations.com |    1962     | 
              
I love to cook with wine.     Sometimes I even put it in the food.
Reply to
Jim Thompson

If it were just the four phases, a sampling phase detector controlling an oscillator at 4f would be one approach. It would potentially be a bit squirrelly, since you'd have to use the VCO as the sampling gate instead of using the reference, but since it's narrowband that wouldn't be a big issue.

You'd need to add additional circuitry to invert the output signal if the transition was negative-going instead of positive-going, because otherwise the instantaneous feedback polarity would be wrong. That's just a single comparator, though, so it ought to be no problem. If only it were so simple.

Unfortunately, QAM has 12 phases: atan(1/3) ~ 18.4 deg, atan(1) = 45 deg, and atan(3)~71.6 deg in the first quadrant, mirrorred in the other four quadrants. They aren't evenly spaced, so frequency multiplication won't work. (There are only 12 phases because there are two constellation points on each of the 45 degree increments.) See e.g.

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.

That "and higher orders" bit worries me some as well.

So I don't think there's a simple analogue way to do this--it'll pretty well have to be full clock recovery.

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs 
Principal Consultant 
ElectroOptical Innovations LLC 
Optics, Electro-optics, Photonics, Analog Electronics 

160 North State Road #203 
Briarcliff Manor NY 10510 

hobbs at electrooptical dot net 
http://electrooptical.net
Reply to
Phil Hobbs

Oh yes, that Red Light District, huh?

Reply to
cameo

Yeah... full of spas and folks who can afford spas and vacations at spas...

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Reply to
DecadentLinuxUserNumeroUno

Specifically, the amplitude information will remain, including the dip to zero during a change between phase states. Hence why I specified a limiter, at least at the input, to discard that. You're probably right, it'd still need one on the output too. Or use a PLL with amplitude-sensitive tracking, so it only pulls during the middle of a symbol when it's the strongest.

Tim

--
Seven Transistor Labs 
Electrical Engineering Consultation 
Website: http://seventransistorlabs.com
Reply to
Tim Williams

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