Some people struggle to try to get an oscillator running in LTspice. This article describes different types of Colpitts and Clap oscillators snd shows how to calculate the component values to get them to run. Crystal oscillators are discussed, along with a method to drastically shorten the startup and settling time in order to view the actual oscillator waveforms.
The descriptions are as brief as possible and omit theory such as Barkhausen stability criterion and other more advanced topics. It is intended to give users confidence that they can get something up and running, then search for more information later as the need arises.
Interesting concept, but the speedup technique in 06.asc don't really work. That is, you have to know the exact answer first, to get a result that is accurate. For example, if .ic vl1c1 is set to say, 0.05 instead of 0.1, it gets a 2V peak signal, and the illusion that that is what it is doing steady state, when in fact if you run it until it eventually stabilises it get to the correct 4V peak.
The standard way to view, essentially the real, accurate voltages, but with fast startup, is to simply De-Q it, by using a larger cs. Typically, one uses a .subckt with parameters to set a XTAL by ro, cp, cs and frequency, by letting the subckt calculate the inductor. De-Quing by a factor of 100 on a cs=10fF would mean you set cs=1p. Characteristics such as loop gain at Fo and phase margin, clipping level and currents all stay the same with the De-Qed circuit.
For phase noise, using a pss/pnoise simulator one can correct for the typical increase 30 db/Dec LF excess noise roll off subtracting the appropriate dB equivalent of the De-Q factor to predict what it does at full Q.
You get the exact answer the first time you run the oscillator and let it settle, as shown in 05.asc.
If you de-Q the circuit, you need to re-establish the original parameters when you want to run AC analysis.
Then when you want to look at the transient response, you have to de-Q it again. This wastes time and increases the chance of error.
If you make a change to the circuit that significantly affects the amplitude, you have to remove the Fast Start condition by adding a semicolon in front of the .IC command, let it settle, get the peak amplitude, then put it back into the Fast Start value.
I did not mention issues like this because I wanted to keep the article as simple as possible to increase the chance that some people would read it. If you go on and blather all day, people will give up. TL;DR.
A question. Why does spice generate such huge currents such as shown in 11.ASC?
I get 2e17 p-p in LTspice IV, and 200 Amps in XVII.
De-Qing doesn't work. As you reduce the Q, the amplitude after settling als o decreases. For example, with CS = 10p, the current through Rs is 17.52 mA p-p instead of the required 20 mA p-p, and the settling time is still to o long, at 55.079 seconds. Here is the LTspice file. Please let me know if you find any errors.
Version 4 SHEET 1 880 680 WIRE 208 48 16 48 WIRE 304 48 208 48 WIRE 336 48 304 48 WIRE -480 64 -496 64 WIRE -352 64 -400 64 WIRE 336 64 336 48 WIRE 16 80 16 48 WIRE -496 128 -496 64 WIRE -432 128 -496 128 WIRE -352 128 -352 64 WIRE -352 128 -368 128 WIRE -160 128 -352 128 WIRE -144 128 -160 128 WIRE 208 160 208 48 WIRE 336 160 336 144 WIRE -544 208 -592 208 WIRE -496 208 -496 128 WIRE -496 208 -544 208 WIRE -480 208 -496 208 WIRE -368 208 -400 208 WIRE -256 208 -288 208 WIRE -240 208 -256 208 WIRE -144 208 -144 128 WIRE -144 208 -176 208 WIRE -128 208 -144 208 WIRE -48 208 -64 208 WIRE 16 208 16 160 WIRE 16 208 -48 208 WIRE 96 208 16 208 WIRE 144 208 96 208 WIRE -592 240 -592 208 WIRE 16 240 16 208 WIRE -496 256 -496 208 WIRE -48 256 -48 208 WIRE 16 320 16 304 WIRE 112 320 16 320 WIRE 208 320 208 256 WIRE 208 320 112 320 WIRE -592 336 -592 320 WIRE -496 336 -496 320 WIRE 16 336 16 320 WIRE 208 336 208 320 WIRE -48 352 -48 336 WIRE 16 416 16 400 WIRE 208 432 208 416 FLAG 16 416 0 FLAG 96 208 Q1B FLAG 112 320 Q1E FLAG -160 128 R7C7 FLAG 304 48 Vcc FLAG -592 336 0 FLAG -496 336 0 FLAG 208 432 0 FLAG 336 160 0 FLAG -544 208 Vout FLAG -256 208 L1C1 FLAG -48 352 0 SYMBOL npn 144 160 R0 WINDOW 3 57 69 Left 2 SYMATTR Value 2N3904 SYMATTR InstName Q1 SYMBOL res 0 64 R0 SYMATTR InstName R2 SYMATTR Value 10k SYMBOL res 192 320 R0 SYMATTR InstName R3 SYMATTR Value 1k SYMBOL voltage 336 48 R0 WINDOW 123 0 0 Left 2 SYMATTR InstName V1 SYMATTR Value 5 SYMATTR SpiceLine Rser=0.1 SYMBOL cap 0 336 R0 SYMATTR InstName C2 SYMATTR Value 390p SYMBOL cap 0 240 R0 WINDOW 3 25 49 Left 2 SYMATTR Value 100p SYMATTR InstName C4 SYMBOL cap -512 256 R0 SYMATTR InstName C5 SYMATTR Value 33p SYMBOL res -608 224 R0 SYMATTR InstName R5 SYMATTR Value 100k SYMBOL cap -64 192 R90 WINDOW 0 0 32 VBottom 2 WINDOW 3 32 32 VTop 2 SYMATTR InstName C7 SYMATTR Value 1n SYMBOL res -384 48 R90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName R7 SYMATTR Value 1E7 SYMBOL cap -176 192 R90 WINDOW 0 0 32 VBottom 2 WINDOW 3 32 32 VTop 2 SYMATTR InstName C1 SYMATTR Value {cs} SYMBOL ind -384 224 R270 WINDOW 0 32 56 VTop 2 WINDOW 3 5 56 VBottom 2 SYMATTR InstName L1 SYMATTR Value {Ls} SYMATTR SpiceLine Rser=0 SYMBOL res -384 192 R90 WINDOW 0 0 56 VBottom 2 WINDOW 3 32 56 VTop 2 SYMATTR InstName R8 SYMATTR Value 10 SYMBOL cap -368 112 R90 WINDOW 0 0 32 VBottom 2 WINDOW 3 32 32 VTop 2 SYMATTR InstName C8 SYMATTR Value 5p SYMBOL res -32 240 M0 SYMATTR InstName R1 SYMATTR Value 10k TEXT -248 -352 Left 2 !.tran 0 50u 0 10p TEXT 192 -352 Left 2 !.options plotwinsize=0 TEXT -248 -384 Left 2 ;'10MHz De-Qed Xtal Osc TEXT 192 -288 Left 2 !.param f=1e7 TEXT 192 -312 Left 2 !.param cs =10p TEXT 192 -264 Left 2 !.param Ls = (0.025330295/f/f/{cs}) TEXT -248 -272 Left 2 ;Total elapsed time: 55.079 seconds TEXT -248 -248 Left 2 ;I(R8) = 17.52 mA p-p
lso decreases. For example, with CS = 10p, the current through Rs is 17.5
2 mA p-p instead of the required 20 mA p-p, and the settling time is still too long, at 55.079 seconds. Here is the LTspice file. Please let me know i f you find any errors.
The frequency is wrong also. It should be 10MHz. It's around 11.5MHz. Somet hing is drastically wrong with this method.
Sure, the frequency is moved by (1 + Cs/2(CL+Cp)), where CL is the xtal load (e.g. in a Colpitts the series value of the caps either side of the xtal), but this is a known correction, and not really a significant factor in the design phase. It can be automatically included in the xtal subcircuit if desired. I wouldn't recommend using a de Q cap of 10p for a 10 fF cs though! Typically I would say 1pF is the max one would want to use for a xtal oscillator.
As I noted, DeQing is the standard way, and it works extremely well, and rationally, it is the only practical way to design high Q oscillators. It keeps the same basic loop gain and phase for starters.
For example, when one actually gets to use the expensive, $100k per seat per year Cadence Periodic Steady State and Phase Noise analysis, for 10 years, one gains a bit of knowledge how oscillators work. :-)
Calculating phase noise is very complicated. Noise at every point of the cycle needs to be determined, so the currents and voltages on DeQed circuits need to be, essentially, the same as the full Q circuit as noise depends on instantaneous currents. Phase noise simulations consistently shows that the low frequency (e.g. 1/f) slope phase noise moves reliably with the DeQed factor. For example if the full Q PN at 10Hz is -100dBc, it is -80dBc with a DeQ factor of 10. HF Flat band noise stays the same whatever the DeQed ratio is.
I have some somewhat original tutorial papers on Oscillator Phase Noise here:
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If I get the time, I will try and address your specific points of your other posts.
Oh dear.... I guess you must have missed posts that explain who I am. I have cut down on my posts though.
... Now for the trumpet.... I am Principle Analog IC Designer at
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There aint a lot of world leading precision, low noise, xtal oscillator vendors. Probably countable on one hand. Its a very niche market. Pretty much no non specialist attempts such oscillators. They are actually somewhat complicated, considering the mere name "Oscillator".
Ovens...linearisers...chebychev compansation functions...DC-DC voltage doubles...LDOs... power compensation... all in a 7 x 5 package...:-)
No it doesn't. One just needs to understand how DeQing effects the results. I already explained some of this.
Just not viable as an only tool in commercial oscillator design. It might have a few uses though.
For example, every time a bias changing component changes, you would need to rerun at high Q to get the exact data to initialise for the fast start.
You do need to pay the money if you want to do accurate phase noise and have it work as designed on first pass silicon. There are no cheapo LTSpices for PSS and Phase Noise analysis.
Today, there is no realistic hope of being competitive in high performance oscillator design without expensive design tools.
Oh.....
I guess you haven't bothered to actually run a comparisons of say, the AC gain/phase through an oscillator Pierce pi network at various Qs. Its actually quite interesting. It just don't matter whether deQ is, the peak gain remains the same.
So, yes, it works wonderfully for AC. Full Q AC makes it really difficult to actually plot and read the data. Way, way to spikey.
I already explained the offset in frequency isn't a problem in a real design. Its a known quantity. Same goes for accurate phase noise, which is what matters. Variation in amplitude is not usually significant. I haven't spent much time investigating why you are getting major amplitude variations in LTSpice. When a 5fF cap is DeQed to 50ff, 500fF, amplitude variation is not normally an issue.
I have ran your circuit in SuperSpice at CS=0.1p with L=2.5m and CS=1p with L=0.25m with cp=1p and both amplitudes are around 4.8V, on a 2ms run However, in LTSpice I get around 2.5V and 4.8V with those same C/L values, so it looks like something is up with LTSpice.
I do note that your example has a pretty big cp at 5pf. Typically is would be 1pF. Even a big 10MHz 3rd overtone is pushing it to be 3pF.
It doesn't. As I explained. It only gives exact data, if it is measures accurately first.
For example, in commercial ASIC designs, ones must do process, temperature and supply corners. For example, see
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Typically, one does 10 thousands of runs for AC and TRAN. The operating conditions are different each time, meaning you don't know how to initialise the fast start. How it actually starts up is also of major significant.
Commercial designs involve a lot more work then running a few sims in LTSpice.
Other issues are, for example, in 3rd Overtone designs. Typically, xtals have an unwanted B mode about 10% higher in frequency than the wanted C mode. This fast start technique, essentially, doesn't allow that part of the B Mode suppression to be evaluated. For vast chunks of a design, the start up behaviour actually needs to be evaluated. This means DeQing for the most part.
I would agree that for setting up spice demos fast starting with this method has some merits.
I normally have you plonked in my regular newsreader due to your idiotic statements. I only see your posts when I visit google groups. I should ignore them.
keeps the same basic loop gain and phase for starters.
In other words...."I made some overbroad statements that were subsequently shown to be somewhat inaccurate, and to which I am not inclined to make a retraction on"
You probably already do. They are in a vast number of products such as sat navs..., comms stuff...
Interesting. It's a lot of work. One of the key issues, is simply having the test equipment. Takes a lot of time and procedures to measure response over temperature in mass production. Thermal mechanics is a big problem. I avoid that bit of it myself...
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