74hc595 shift registers, what am I doing wrong?

Are you using a pullup on the 2N7000? I'm assuming the transistor is being used as a pulldown, I didn't look up what type of part it is. Is this a FET or a BJT?

If the 2N7000 is a FET the threshold might be too high to trigger from a

3.3 volt source.

If you replace the HC595 with an HCT595 it should work without the transistor. HCT has TTL level input thresholds (between 0.8 and 2.0 volts) which are within the range of 3.3 volt CMOS drive. HC has 5 volt CMOS voltage levels which are a bit marginal when driven by 3.3 volt logic.

--

Rick

Yes, I have a pullup resistor on the 2N7000. I'm basically using the level shifter schematic here:

It's a popular circuit, particularly when using I2C.

I'll see if I have any HCTs laying around.

Yes, I do this on a board I produce, but use a product designed for the job called a "quickswitch". I'm not sure of your schematic. It looks like it should work, but the switching speed won't be so fast. With the gate at 3.3 volts, the FET will stop conducting the 3.3 volt drive signal as the voltage on the 5 volt side approaches 3.3 volts minus the gate threshold voltage which is 2.1 volts typ. So at 1.2 volts the 5 volt side has lost it's drive and the 10 kohm pullup is the only thing driving the signal. This will be *slow* and may be causing noise problems on the ramp up.

I have seen recommendations that the gate be tied to the 5 volt rail through a diode. This removes the drive in either direction before the signal reaches 3.3 volts protecting the rPi. The gate-diode connection should be pulled down with a 10 kohm resistor. I would also change the

10 kohm resistor on the 5 volt side to 1 kohm.

Heck with a 2.1 volt threshold you might not even need the diode or at least use a Schottky diode.

--

Rick

Do you have bypass caps on each chip?

Do you have terminations on the clock inputs to the chips?

What is the physical connection between the Pi and your circuit?

74HC parts are fast, and even a foot-long run between a clock source and a clock input will cause double-clocking or worse if the clock isn't terminated. If it's a few inches all on one board then you're probably OK, or if you're using a chip with controlled rise times. Otherwise -- terminate.

Lack of a good ground reference (and I mean a ground plane or twisted pairs) will cause weird cross-talk issues; since the 74HC parts are fast, they'll catch them all.

Finally, failing to use bypass caps at the chips will leave you open to the supply voltage bouncing, which will couple into the chips, which, again, will mess things up. You want to use 100nF caps, one per chip, right at the end of the chip and with short leads to the power and ground pins.

Your problem may be none of these things, but making sure you have bypassing, terminations and good ground references is more or less imperative.

--
www.wescottdesign.com

Do you shift out the data on correct clock edge? I currently don't know on which edge the 595 shifts, but you should make sure you change the data on the opposite edge.

--
Reinhardt

1) You *do* need a level-shifter to drive the 5v logic from the 3.3v rPi. 2) The one you're using is too slow.

A cheesy fudge would be to change the 10k 5v pullup to 3.3k so you can drive more capacitance (more 'hc595s).

An honest fix would be to use a gate (from a suitable logic family) to translate the 3.3v rPi signals to 5v levels.

(Hopefully this is on a PCB board, not strung together like spaghetti, right?)

Cheers, James Arthur

up in either a 3-chip or 6-chip configuration. I'm driving them with a ras pberry pi. They're driven with three pins: data, clock, and latch. Data is daisy-chained from chip to chip. Clock and latch are common to all chips. T he latches are powered via 5V. The raspberry pi is a 3.3V device.

puts) with 3 shift registers. It's greatly unstable with 6 shift registers. I get numerous errors on the outputs. Sometimes I get random gibberish.

figuration go wonky. 10X scope probe is fine.

V logic, I tried installing a 2N7000 based level shifter on the clock and l atch pins (since those are the ones common to all chips, and thus affected by adding more registers). There's nice clean 5V clock pulses now, but if a nything it made the problem worse.

Use 74HCT595s instead of 74HC595 and then you won't need level shifters. Th e HC family uses CMOS logic levels while the HCT family uses TTL logic leve ls. The Voh of the 3.3V rPI is 2.4V. HCT will recognize voltages above 2.0 volts as high. HC Voh could be over 3 volts with a 5 volt power supply.

em up in either a 3-chip or 6-chip configuration. I'm driving them with a r aspberry pi. They're driven with three pins: data, clock, and latch. Data i s daisy-chained from chip to chip. Clock and latch are common to all chips. The latches are powered via 5V. The raspberry pi is a 3.3V device.

utputs) with 3 shift registers. It's greatly unstable with 6 shift register s. I get numerous errors on the outputs. Sometimes I get random gibberish.

onfiguration go wonky. 10X scope probe is fine.

5V logic, I tried installing a 2N7000 based level shifter on the clock and latch pins (since those are the ones common to all chips, and thus affecte d by adding more registers). There's nice clean 5V clock pulses now, but if anything it made the problem worse.

The HC family uses CMOS logic levels while the HCT family uses TTL logic le vels. The Voh of the 3.3V rPI is 2.4V. HCT will recognize voltages above 2.

0 volts as high. HC Voh could be over 3 volts with a 5 volt power supply.

That's a good idea.

As an alternative using parts he already has, here's a faster clock buffer:

+5v +5v --- --- | | 1k [R2] [R4] 1k | | | +---> clk5v +--. | | | ||--' Q2 BSS123 / Q1 ||--' | ||

Oops, the 2n7000 isn't suitable. It's only guaranteed to conduct

1mA @ Vgs=3v. It's also pokey.

Cheers, James Arthur

l shifter schematic here:

ctional-level-shifter/. It's a popular circuit, particularly when using I2C .

Or GALs, which can handle 3V logic.

I tried something similar with SRs years ago and had similar problems. I e nded up using a single CPLD with 32 I/Os driving 4 7-segments LEDs. With s ingle chip, the timing, noise and xtalk are easier to manage, but power is not. With close to 500mA on a single chip, thermo management is difficult.

I will soon have to revisit this issue, but with a few GALs. For simplicit y, I am combining the BLDC and SR into one chip. Namely, it's a BLDC contr oller if D9 is high and SR if D8 is high. All the GALs will be programmed identically and only once. I only need 3 GALs, so it might be doable. Can you use two independent chains of 3 chips each? Are you really that tight on RPi pins?

See LevelTranslator.pdf on the S.E.D/Schematics Page of my website.

This example is demonstrated at 5V logic swing input and 12V output, but will work at 3.3V (VDD) input, 5V (VCC) output.

===>> The 2N2369 device is selected since it's gold-doped and recovers quickly from saturation. Non-gold-doped devices may not be fast enough for your application, depending on your logic pulse widths. ...Jim Thompson

--
| James E.Thompson                                 |    mens     | 
| Analog Innovations                               |     et      | 
| Analog/Mixed-Signal ASIC's and Discrete Systems  |    manus    | 
| San Tan Valley, AZ 85142     Skype: skypeanalog  |             | 
| Voice:(480)460-2350  Fax: Available upon request |  Brass Rat  | 
| E-mail Icon at http://www.analog-innovations.com |    1962     | 
              
I love to cook with wine.     Sometimes I even put it in the food.

m up in either a 3-chip or 6-chip configuration. I'm driving them with a ra spberry pi. They're driven with three pins: data, clock, and latch. Data is daisy-chained from chip to chip. Clock and latch are common to all chips. The latches are powered via 5V. The raspberry pi is a 3.3V device.

tputs) with 3 shift registers. It's greatly unstable with 6 shift registers . I get numerous errors on the outputs. Sometimes I get random gibberish.

nfiguration go wonky. 10X scope probe is fine.

5V logic, I tried installing a 2N7000 based level shifter on the clock and latch pins (since those are the ones common to all chips, and thus affected by adding more registers). There's nice clean 5V clock pulses now, but if anything it made the problem worse.

ers

That works as long as the OP understands it's inverting.

I was concerned the edges were too slow for the 74hc595, and that the OP was possibly using a wimpy i2c output from the rPi.

Here's an easy patch that covers all the bases:

+5v --- | |\| |\ dat3v3 >---| >O---| >o---> dat5v |/ |/

|\ |\ clk3v3 >---| >O---| >o---> clk5v |/ |/

|\ |\ ltch3v3 >--| >O---| >o---> ltch5v |/| |/ | 74hct14 ===

Cheers, James Arthur

The shift registers are on PCBs, three registers per board, with right angl e headers between the boards (that's how I can easily unplug one and go fro m 6 registers to 3).

The boards have about a foot of wire between them and the pi.

I've tried a few different clocks, ranging from 1ms to about 20ms. I do hav e a delay between setting the data bit and toggling the clock, and a delay after toggling the clock before setting the next data bit. I don't need spe ed out of this thing, so I'm fine with setting it slow.

I do have 0.1uf bypass caps at the shift registers. I've put a scope on the 5V rail on the boards and it looks good.

I haven't 'terminated' the clock line. How should I do that? Throw a resist or on at the end of the chain? What value? That would be pretty easy to do.

Daisy-chained shift registers are tricky. At clock time, the output of each SR changes, but the *old* output level of stage N has to be clocked into the input flop of N+1. A small error in clock timing can mess up this handoff.

If your clock has a slow rising edge, different chips can interpret the instant-of-clocking wrong, and the bit handoff will fail. And if your clock rings or has a plateau, ditto.

So a string of SR chips will need a hard, fast, clean clock.

3.3 volts is marginal to clock an HC595 that's running at 5 volts. That amplifies the clock hazard.

One workaround is to add delays in the data path. That can be as simple as adding gate delays, or an RC, or even just a capacitor to ground, to the Dout/Din paths between the chips. But a good clock is a more elegant solution.

When we drive a 595 string from an ARM chip, we use a clock buffer, 5 volt swing when appropriate, and end terminate. The clock trace should be controlled impedance and run linearly (no branching) from the first chip in the string to the last, then terminated.

This is, incidentally, just about he worst possible digital circuit to build on one of those awful plastic breadboards.

--

John Larkin         Highland Technology, Inc 

jlarkin att highlandtechnology dott com 
http://www.highlandtechnology.com

Things that might be useful that I do have readily available in the junk box, that I could use tonight without having to order something and wait:

• 74LS04 hex inverters

• 2N3906 PNP and 2N4401 NPN transistors (Jim, would the 2N4401 substitute into your level converter schematic?)

• 4N25 opt-isolators

• ULN2803 darlington drivers

Really? I didn't know that >:-}

It _doesn't invert.

If the clock is positive going _and_ short, the overlap current should not be a problem... if the clock is long you could be lucky, or maybe not.

If you want a digital solution there's several chips specifically made for such applications, such as...

SN74AVC4T774 ...Jim Thompson

--
| James E.Thompson                                 |    mens     | 
| Analog Innovations                               |     et      | 
| Analog/Mixed-Signal ASIC's and Discrete Systems  |    manus    | 
| San Tan Valley, AZ 85142     Skype: skypeanalog  |             | 
| Voice:(480)460-2350  Fax: Available upon request |  Brass Rat  | 
| E-mail Icon at http://www.analog-innovations.com |    1962     | 
              
I love to cook with wine.     Sometimes I even put it in the food.

Possibly, if your pulse lengths are long enough to exceed storage time.

Give it a try.

...Jim Thompson

--
| James E.Thompson                                 |    mens     | 
| Analog Innovations                               |     et      | 
| Analog/Mixed-Signal ASIC's and Discrete Systems  |    manus    | 
| San Tan Valley, AZ 85142     Skype: skypeanalog  |             | 
| Voice:(480)460-2350  Fax: Available upon request |  Brass Rat  | 
| E-mail Icon at http://www.analog-innovations.com |    1962     | 
              
I love to cook with wine.     Sometimes I even put it in the food.

No.

You could use the 74ls04's, the others are too slow. Add a 1k pull-up resistor to +5v on each 74ls04 output.

A foot of wire between boards is not a happy thing, but probably manageable. For starters you might want to add 75 ohms in series with the rPi clock output.

What does the rPi driver look like (i.e., open drain? i2c? How fast, how strong) and how fast are you clocking the data out to the hc595's?

Cheers, James Arthur

m up in either a 3-chip or 6-chip configuration. I'm driving them with a ra spberry pi. They're driven with three pins: data, clock, and latch. Data is daisy-chained from chip to chip. Clock and latch are common to all chips. The latches are powered via 5V. The raspberry pi is a 3.3V device.

tputs) with 3 shift registers. It's greatly unstable with 6 shift registers . I get numerous errors on the outputs. Sometimes I get random gibberish.

nfiguration go wonky. 10X scope probe is fine.

5V logic, I tried installing a 2N7000 based level shifter on the clock and latch pins (since those are the ones common to all chips, and thus affected by adding more registers). There's nice clean 5V clock pulses now, but if anything it made the problem worse.

ch SR changes, but the *old* output level of stage N has to be clocked into the input flop of N+1. A small error in clock timing can mess up this hand off.

nstant-of-clocking wrong, and the bit handoff will fail. And if your clock rings or has a plateau, ditto.

Yes, i gave up on the clock race and just used a single 32 outputs CPLD. T hey already have the clocking worked out.

marginal to clock an HC595 that's running at 5 volts. That amplifies the c lock hazard.

s adding gate delays, or an RC, or even just a capacitor to ground, to the Dout/Din paths between the chips. But a good clock is a more elegant soluti on.

t swing when appropriate, and end terminate.

How many chips did you managed to daisy chain?

hing) from the first chip in the string to the last, then terminated.

Shouldn't it be from the last chip to the first? You want the last chip to change state first.

ild on one of those awful plastic breadboards.